Chapter 1: Two Real Sample Designs & the 17-Phase SCADA Workflow

Typical SCADA system architecture diagram showing the enterprise layer, supervisory SCADA layer, communication layer, and field layer with RTUs, PLCs, and intelligent electronic devices

Typical SCADA system block diagram showing enterprise applications, SCADA level with servers and workstations, communication network, and field level with RTUs, PLCs, and field devices

Comparison table of SCADA, DCS, and PLC platforms across architecture, control philosophy, typical scale, redundancy, and best-fit applications

ISA-5.1 P&amp;ID symbology chart showing field-mounted, panel-mounted, and DCS/PLC instrument bubble symbols, common instrument function letters, line symbology, and tag number format examples

Standard I/O list format showing columns for tag, description, I/O type, signal range, PLC rack/slot/channel, scaling, engineering units, fail state, and alarm limits with sample rows

Modbus register map showing coils, discrete inputs, input registers, and holding registers with their address ranges, sample data mappings, and slave device memory layout

Industrial protocol comparison table across Modbus, DNP3, OPC-UA, EtherNet/IP, PROFINET, and HART showing media, topology, addressing, typical use case, and security capabilities for each

PLC scan cycle diagram showing the four continuously repeated steps read inputs, execute program, write outputs, and housekeeping, with input and output image tables and interrupt/event task handling

Ladder diagram for a classic motor start/stop seal-in latch control circuit showing start and stop pushbuttons, a motor output coil, and a seal-in auxiliary contact with addressing legend

Sequential function chart for a batch reactor process showing steps init, fill, heat, react, drain, and clean connected by transitions, with IEC 61131-3 action qualifiers and a steps overview table

P, I, and D term contributions diagram showing the response of the proportional, integral, and derivative terms individually to a step change in error, with equations and time response graphs for each

FAT versus SAT checklist comparing factory acceptance test and site acceptance test across what is verified, who witnesses the test, documentation required, and punch list resolution process