A 40-section, image-first interactive guide tracing a custom RISC processor's complete journey from RTL through FPGA prototyping, ASIC synthesis and physical design, signoff, tape-out, and first-silicon bring-up — with 21 real design-flow diagrams covering the RTL-to-GDSII flow, RTL processor architecture, synthesis mapping, physical design and clock tree synthesis, DRC/LVS signoff, GDSII layer geometry, tape-out, and semiconductor fabrication.
13 chapters follow one case study end to end: the RTL-to-GDSII process overview, RTL as the single source of truth, FPGA synthesis and place & route, FPGA programming and prototype bring-up, RTL design using VHDL and CAD tools, why FPGA success never equals ASIC readiness, the ASIC readiness review, ASIC synthesis, physical design (floorplanning, power planning, placement, clock tree synthesis, routing), signoff (timing, power, DRC, LVS), GDSII generation and tape-out, first silicon bring-up, and lessons learned/errata/iteration. Four illustrated appendices close the guide: how VHDL fits into the real ASIC flow, a complete artifact-level map of a simple IC, FPGA vs. ASIC positioning, and RTL fundamentals.
Use the Prev / Next buttons at the bottom, or the arrow keys on your keyboard. Click the ☰ menu button in the top-right to open the table of contents and jump to any section. Chapters with multiple diagrams — physical design, signoff, and GDSII generation each get several dedicated figure slides — so every diagram stays large enough to read its labels clearly.
Hardware engineers transitioning from FPGA-only work to ASIC execution, startup hardware teams building their first custom silicon, system architects who need to understand ASIC execution risk, and software engineers working closely with silicon teams who want a process-level mental model of how a chip actually goes from RTL to manufactured silicon — not just a features tour of EDA tools.
13 chapters plus 4 illustrated appendices following a custom RISC processor from specification and RTL through FPGA prototyping, the FPGA-to-ASIC transition, ASIC synthesis, physical design, signoff, GDSII generation, tape-out, first silicon bring-up, and post-silicon iteration — 21 real design-flow diagrams across 40 sections.
FPGA is not required to build an ASIC, but it is one of the most effective ways to reduce functional and system-level risk before committing to manufacturing. The guide dedicates two full chapters (6A and 6B) specifically to why FPGA success proves functional correctness but never proves ASIC timing, power, or manufacturability.
Both start from the same RTL, but FPGA synthesis maps logic onto pre-fabricated LUTs, flip-flops, and block RAM with programmable, pre-engineered clock networks, while ASIC synthesis maps the same RTL onto real standard cells — NANDs, NORs, inverters, and flops — where every buffer costs real silicon area and power, and wire delays dominate rather than being routed around automatically.
Timing signoff (static timing analysis across voltage, temperature, and process corners), power signoff (dynamic power, leakage, IR drop, electromigration), DRC (design rule checking against foundry manufacturing rules), and LVS (layout vs. schematic connectivity verification). All four must pass — passing three is a failure.
Only the GDSII (or OASIS) file, layer maps, test structures, documentation, and packaging requirements. The foundry never receives RTL, VHDL, netlists, testbenches, or simulation data — GDSII is the single source of manufacturing truth.
Disclaimer: This guide summarizes general ASIC/FPGA design-flow concepts and an illustrative RISC processor case study for educational purposes only. It is not a substitute for vendor EDA tool documentation, foundry design rules, or professional engineering review. Always validate any real tape-out against your foundry's process design kit and your own signoff criteria.