A 20-section interactive reference covering chip-level electronics engineering end to end: digital logic fundamentals and Boolean algebra, Verilog vs VHDL, FPGA architecture (LUTs, CLBs, DSP slices), the FPGA and ASIC design flows through RTL to GDSII, semiconductor manufacturing from crystal growth to lithography to packaging, PN junction and transistor device physics, analog op-amp design, power converter topologies, signal integrity for high-speed design, embedded systems architecture (MCU/MPU/SoC), memory hierarchy, and PCB design basics for digital circuits.
The guide is organized around the full path from a logic equation to packaged silicon. Sections 2–4 cover digital logic fundamentals — gates, Boolean algebra, combinational circuits (adders, multiplexers, decoders), and sequential circuits (latches, flip-flops, registers, counters, finite state machines, and setup/hold timing). Sections 5–8 cover hardware description languages (Verilog vs VHDL vs SystemVerilog), FPGA architecture (LUTs, CLBs/LABs, programmable interconnect, DSP slices, block RAM), the FPGA design flow (synthesis, place-and-route, bitstream generation), and the nine-stage ASIC design flow from specification through tape-out. Sections 9–11 cover semiconductor manufacturing — crystal growth via the Czochralski process, photolithography and EUV vs deep-UV, doping/etching/deposition, and packaging, test, and fab economics. Sections 12–15 cover PN junction and diode physics, BJT and MOSFET device physics, analog op-amp topologies, and power converter design (the buck converter in depth). Sections 16–19 cover signal integrity, embedded systems architecture (MCU vs MPU vs SoC), memory hierarchy, and PCB design basics. Section 20 is a quick-reference formula and constants sheet.
Use the Prev / Next buttons at the bottom, or press the arrow keys on your keyboard. Click the ☰ menu button in the top-right corner to open the table of contents and jump directly to any of the 20 sections. The teal progress bar at the top tracks your position through all sections. Scroll the mouse wheel to advance or go back.
This handbook is deliberately sequenced to mirror how a real digital design becomes physical hardware. A design starts as Boolean logic (gates, combinational and sequential circuits), gets described in an HDL like Verilog or VHDL, and is mapped either onto reconfigurable FPGA fabric (LUTs and CLBs, synthesized into a loadable bitstream) or through the far more expensive ASIC flow (RTL synthesized into a fixed gate-level netlist, physically placed and routed, verified, and taped out as GDSII for fabrication). The manufacturing sections then explain what actually happens inside the foundry — crystal growth, lithography, doping — to turn that GDSII file into working transistors on a wafer. The device physics, analog, and power sections explain the transistor-level behavior those manufacturing steps produce, and the signal integrity, embedded systems, memory, and PCB sections cover how those chips are actually deployed and connected together on a real board.
Worked numerical examples are included for the diode equation, BJT and MOSFET current equations, op-amp gain-bandwidth and slew-rate sizing, and buck converter component sizing and efficiency — each intended to be reproduced by hand as a sanity check on a real design. When applying the op-amp worked example, always verify both the gain-bandwidth product and the slew rate against your actual signal frequency and amplitude; a part can have ample bandwidth margin and still distort a signal if its slew rate is too low. When applying the buck converter formulas, confirm the converter is actually operating in continuous conduction mode (CCM) before relying on the simple V_out/V_in = D relationship, since light loads can push a converter into discontinuous conduction mode (DCM), where output voltage becomes load-dependent.
An FPGA is built from generic reconfigurable logic elements (look-up tables and configurable logic blocks) plus programmable interconnect, with no fixed function until a configuration bitstream is loaded — it can be reprogrammed in the field. An ASIC is a fixed-function chip whose logic is permanently defined at fabrication; it cannot be reconfigured after tape-out. ASICs require very high non-recurring engineering (NRE) cost — mask and tooling costs alone can run into the tens of millions of dollars — but achieve much lower per-unit cost, size, and power at high production volume. FPGAs are the standard choice for prototyping, low/mid-volume production, and designs still expected to change.
Verilog (IEEE 1364), developed in 1984, has C-like syntax, is loosely typed and terse, and is historically dominant in the US commercial ASIC/FPGA industry. VHDL (IEEE 1076), developed in the early 1980s for the US Department of Defense, has Ada-based syntax, is strongly and strictly typed, is more verbose, and is more common in Europe and in aerospace/defense/safety-critical work. Both describe hardware that operates concurrently, not sequentially, and both have a synthesizable subset that differs from what a simulator will accept — mixing up blocking and non-blocking assignment forms in clocked logic is one of the most common bugs in either language.
The flow runs through nine stages: specification, RTL design, functional verification, logic synthesis (RTL to a gate-level netlist using the foundry standard cell library), floorplanning, place and route, timing closure across process/voltage/temperature corners, physical verification (Design Rule Check and Layout Versus Schematic), and tape-out, where the final layout is exported as GDSII files and sent to the foundry. A bug found after tape-out requires a costly mask re-spin, which is why functional verification often consumes more engineer-time than RTL design itself.
Sand (silicon dioxide) is reduced to metallurgical-grade silicon and then purified to electronic-grade polysilicon at 99.9999999% purity. A single-crystal ingot is grown by the Czochralski process and sliced into wafers (commonly 200mm or 300mm). Photolithography (using deep-UV or, at leading-edge nodes, 13.5nm EUV light) patterns each layer, followed by repeated cycles of etching, doping (ion implantation), and deposition (CVD or PVD) to build up the transistor and interconnect stack. Finished dies are electrically tested on the wafer, diced, and packaged via wire bonding or flip-chip before final test.
A microcontroller integrates a CPU core, RAM, flash, and peripherals on one die, boots directly into firmware with no OS, and offers deterministic timing (examples: STM32, AVR). A microprocessor is essentially just a CPU core with no significant on-chip memory, depending on external DRAM and storage and requiring a full OS such as Linux (examples: ARM Cortex-A parts, x86). A system-on-chip integrates a multi-core CPU, GPU, and memory controller on one die but still needs external DRAM/storage and a full OS (examples: Raspberry Pi 5, Qualcomm Snapdragon). Some parts like the ESP32 blur this line, integrating CPU, RAM, and radio hardware on-die while still running bare-metal or lightweight RTOS firmware like an MCU.
Disclaimer: This reference guide summarizes publicly available engineering standards and principles for educational purposes only. Always consult the official adopted edition of the applicable standard or datasheet for design, engineering, and compliance decisions. Standards referenced herein are copyright their respective organizations (IEEE, JEDEC, ASME, IPC, etc.).