Input Scan → Program Execution → Output Update → Housekeeping · Live I/O & ladder
When to use: Use this to understand how a PLC executes a program. A PLC does not react instantly — it repeats a fixed scan cycle: it reads all physical inputs into an image table, executes the ladder logic top-to-bottom using that frozen snapshot, then writes results to physical outputs. Toggle the field inputs, then Run or single-Step to watch each phase and the live I/O states. The example program is a motor seal-in latch with a 3-second TON start delay and an E-Stop interlock.
The PLC scan cycle is the fundamental execution model of all programmable logic controllers: the PLC does not respond instantly to field inputs but instead repeats a fixed sequence of reading all inputs, executing all logic, and writing all outputs in a continuous loop. Understanding this cycle is essential for diagnosing timing-dependent faults, designing high-speed interlocks, and understanding why output responses can lag behind input changes by up to one full scan time.
Every PLC scan consists of four phases. Phase 1 (Input Scan): the PLC reads all physical digital and analog inputs and copies their current state into the input image table — a memory snapshot. Phase 2 (Program Execution): the PLC executes the user program (ladder logic, function block diagram, structured text) top-to-bottom using the frozen input image table, not the live inputs. All computations and logic evaluations use this snapshot. Phase 3 (Output Update): the PLC writes the output image table (computed results) to the physical output terminals, energizing or de-energizing connected devices. Phase 4 (Housekeeping): the PLC handles communications requests, system diagnostics, and internal timers.
The critical implication is that an input change that occurs between the end of Phase 1 and the beginning of the next Phase 1 will not be seen until the next scan. For a 20 ms scan time, an input pulse shorter than 20 ms may be missed entirely. Time-critical tasks — safety interlocks, high-speed counting — must be handled in interrupt routines that preempt the scan cycle.
IEC 61131-3 (International Standard for PLC Programming Languages) defines the software model for all PLC platforms, including the scan cycle execution model and the five standard programming languages: Ladder Diagram (LD), Function Block Diagram (FBD), Structured Text (ST), Instruction List (IL, deprecated), and Sequential Function Chart (SFC). IEC 61131-3 also defines time-driven task types: cyclic tasks (the main scan), periodic tasks, and event-driven interrupt tasks. For safety applications, IEC 62061 and IEC 61511 require that safety function response times are analyzed against the process demand rate and the PLC scan time.
Scan time increases proportionally with the amount of program code and the number of I/O points. A typical PLC scan for a mid-sized application (1000 rungs, 500 I/O points) is 5–20 ms. Scan times above 50 ms can cause visible delays in HMI response and can miss fast process events. To keep scan time acceptable, move computationally intensive tasks (floating-point math, PID algorithms, data logging) to lower-priority periodic tasks that execute every 100 ms or 1 second, preserving the fast scan for I/O update and critical interlocks.
High-speed counters (HSC) and pulse-width modulation (PWM) outputs are handled in hardware by the PLC I/O module itself, bypassing the scan cycle entirely. These can count or pulse at MHz rates regardless of the scan time. For safety applications, the PLC safety function response time = input filter time + scan time + output filter time; this must be less than the process safety time (PST) determined by the hazard analysis.
The simulator runs a small ladder program: a motor seal-in latch (Start/Stop/E-Stop logic using M0 internal bit), a 3-second TON timer (T0), and three output rungs (Q0 motor, Q1 run lamp, Q2 delay lamp). Toggle the field inputs (Start PB, Stop PB, E-Stop) before or during the scan. Click Run to execute continuously at the configured scan rate, Step Phase to advance one phase at a time, or Reset to clear all states. Observe how changing an input during Phase 2 (Program Execution) is not seen until the next Input Scan — the hallmark of the scan cycle.
A typical PLC scan time for a mid-sized industrial application is 5–20 ms. Scan time is affected by: the number of I/O points (input scan time increases linearly), program size and instruction type (floating-point and PID instructions take longer than bit-level logic), communications processing (polling HMI/SCADA adds variable time), and PLC processor speed. High-end PLCs (AB ControlLogix, Siemens S7-1500) can execute large programs in 1–5 ms; small PLCs (AB Micro820) may take 10–50 ms.
The input change is not seen until the next scan's input scan phase. The current scan executes entirely using the input image table snapshot taken at the start of the scan. This means the maximum response time to an input change is two scan times (worst case: change occurs immediately after the input scan, then the next scan also executes before the updated value reaches the output). For a 20 ms scan, worst-case response is 40 ms.
A seal-in rung is a ladder logic pattern that maintains a coil energized after a momentary push-button is released. The rung is: (NO Start contact OR NO M0 contact) AND NC Stop contact → M0 coil. Once M0 is energized by Start, the parallel M0 contact maintains the coil even after Start is released. The Stop contact (normally closed in the rung, opened by pressing Stop) breaks the seal-in circuit, de-energizing M0. This pattern is the fundamental motor start/stop interlock in all industrial PLC programs.
Interrupt routines (Selectable Timed Interrupts, STI, in Allen-Bradley; Organization Blocks, OB, in Siemens) preempt the main scan cycle when triggered by a timer, input edge, or fault event. The CPU suspends the main program, executes the interrupt routine to completion, then resumes the main program from where it was interrupted. Interrupt routines are used for: fast I/O response (STI at 1 ms for PID), fault handling, communication synchronization, and high-speed counter reset.
The input image table is a memory copy of all physical input states taken at the beginning of the scan (Phase 1). During program execution (Phase 2), all logic instructions that reference inputs read from this memory image, not the live terminal state. This ensures that the program sees a consistent, stable set of input values for the entire scan even if physical inputs change during program execution. The image table for outputs works in reverse: logic writes to the output image memory, and Phase 3 copies this image to the physical terminals.
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