Why a chip still burns power even when it's not switching.
Ask most people what makes a chip consume power and they'll describe something like computation — gates flipping, signals toggling, work happening. That's real, and it's the power most people intuitively picture. But it's only half the story, and in modern advanced process nodes it isn't even the bigger half anymore. A CMOS chip sitting completely idle, with no gates switching at all, still draws real, non-zero power — purely from being powered on. CMOS power splits cleanly into two physically distinct mechanisms: dynamic power, consumed only during a switching transition, and static (leakage) power, consumed continuously regardless of switching activity. Confusing the two — or assuming the second one is negligible — is exactly what leads engineers astray when a design that looks efficient on paper runs hot and drains a battery while doing nothing at all.
Every CMOS gate output drives some load capacitance C — the input capacitance of the next gate, plus wiring and via parasitics. Each time that output switches from 0 to 1, the supply has to push charge onto C, charging it to VDD. Each time it switches back from 1 to 0, that same charge drains to ground instead of doing any useful work. That charge-and-discharge cycle is the entire physical origin of dynamic power: Pdynamic ≈ C·V2·f, where f is how often the gate actually switches. Triple the switching frequency and dynamic power triples with it. Double the supply voltage and it quadruples. Critically, if a gate never switches at all, its dynamic power is exactly zero — there is no charge movement to pay for.
A real transistor that's nominally "off" is never truly an open circuit. Small leakage currents — subthreshold leakage sneaking under the threshold voltage, and gate leakage tunneling straight through the gate oxide — keep flowing even in a gate that's sitting perfectly still in a stable logic state, with nothing switching at all. That's static power, also called leakage power: it doesn't care whether the chip is computing or idle, because it isn't caused by switching in the first place — it's a property of the transistor itself, present continuously the moment the chip is powered on. In older, larger process nodes this leakage was small enough to treat as a rounding error next to dynamic power. It hasn't stayed that way: shrinking transistors pack far more of them into the same area, use thinner gate oxides, and rely on lower threshold voltages to stay fast — and all three of those trends increase leakage. In modern advanced process nodes, static power has grown into a significant, sometimes dominant, share of total chip power.
Because dynamic and static power come from two physically different mechanisms — charge movement during a transition versus continuous leakage through an imperfect switch — no amount of reducing switching frequency, clock gating, or trimming activity factor does anything to the static term. That's exactly why modern low-power chip design carries two separate toolkits. Power gating physically disconnects the supply rail from an idle block using a header or footer switch, cutting its leakage path essentially to zero — something reducing its switching activity alone can never do, since a block with zero switching still leaks continuously as long as it stays powered. Multi-threshold-voltage (multi-Vt) cell libraries attack the same problem from the transistor-selection side: fast, high-leakage, low-Vt cells are used only on the timing-critical paths that truly need the speed, while slower, low-leakage, high-Vt cells fill everywhere else, trading a little speed for a large cut in standby leakage. Both techniques exist specifically because static power needed its own countermeasures once it stopped being a rounding error.
False — and increasingly so at every new process node. It's true that dynamic power collapses to zero for a gate that never switches, since there's no charge movement to pay for. But static/leakage power doesn't depend on switching at all; it's a continuous side effect of the chip simply being powered on, flowing through billions of nominally "off" transistors whether they're doing anything useful or not. In older, larger process nodes this leakage was small enough to ignore. In modern advanced nodes — with thinner gate oxides, lower threshold voltages, and vastly more transistors packed into the same area — it has grown into a significant, sometimes dominant, share of total chip power. That's precisely why techniques like power gating — physically removing power from idle circuit blocks, rather than merely reducing how often they switch — are considered essential, not optional, in modern low-power design. Reducing switching activity is a real and useful lever, but it only ever addresses the dynamic half of the power budget.
Explains why a CMOS chip consumes power through two physically distinct mechanisms — dynamic power, paid only when a gate actually switches state, and static (leakage) power, drawn continuously just from being powered on — and why leakage has grown from a rounding error in older process nodes into a significant, sometimes dominant, share of total chip power in modern advanced nodes.
Power consumption intuitively maps onto activity — a chip doing more work should use more power, and a chip doing nothing should use close to none. That intuition correctly describes dynamic power, which really is proportional to switching activity and drops to zero for a gate that never transitions. It fails for static power, which isn't caused by switching at all — it's leakage current flowing continuously through transistors that are nominally 'off,' present the instant the chip is powered on regardless of whether anything is computing. Treating total power as if it were only the dynamic term is exactly the mistake that makes an idle design run hotter, and drain a battery faster, than expected.
Dynamic power comes from charging and discharging the load capacitance C at each gate output every time it switches: P_dynamic ≈ C·V²·f, where f is switching frequency. It scales linearly with capacitance and frequency and with the square of supply voltage, and it is exactly zero for a node that never transitions. Static power comes from subthreshold leakage (current that sneaks through a transistor below its nominal threshold voltage) and gate leakage (current tunneling directly through an ultra-thin gate oxide), both of which flow continuously in every powered-on transistor independent of its logical switching state. Shrinking process nodes increase both leakage mechanisms — thinner gate oxides raise tunneling current, lower threshold voltages (needed to keep transistors fast at lower supply voltages) raise subthreshold leakage exponentially, and far higher transistor density multiplies the total leakage contribution across the whole chip.
The practical consequence is that a chip sitting completely idle — no switching activity, in theory zero dynamic power — still draws real, non-zero static power purely from being powered on, and in an advanced process node that static draw can rival or exceed the dynamic power the chip uses while actively working. This is exactly why modern low-power design relies on power gating (physically cutting the supply to unused blocks with a header/footer switch, driving their leakage close to zero) and multi-threshold-voltage cell libraries (reserving fast, leaky, low-Vt transistors only for timing-critical paths, using slower, low-leakage, high-Vt transistors everywhere else). Neither technique is about reducing switching activity — they exist because reducing switching activity alone cannot touch the static term.
Yes — the terms are used interchangeably. Both refer to the power drawn by a CMOS circuit independent of switching activity, arising from subthreshold and gate leakage currents in nominally "off" transistors.
Three compounding effects: gate oxides get thinner, which increases direct-tunneling gate leakage; threshold voltages get lower (needed to keep transistors fast as supply voltage drops), which increases subthreshold leakage roughly exponentially; and transistor density increases sharply, multiplying the total leakage contribution across the chip even before accounting for the per-device increase.
No. Clock gating stops a block from switching, which eliminates its dynamic power, but the transistors in that block remain powered and continue to leak exactly as before. Only removing the supply voltage itself — power gating — addresses the static/leakage term.
It is a standard-cell library offering the same logic gates built with multiple transistor threshold voltages. Low-Vt cells switch faster but leak more; high-Vt cells leak far less but switch more slowly. Chip designers assign low-Vt cells only to the small fraction of paths that are actually timing-critical and use high-Vt cells everywhere else, cutting total leakage substantially without sacrificing the performance the design actually needs.
Yes — that is precisely the idle-chip case. A block with no switching activity at all has zero dynamic power by definition, since P_dynamic ≈ C·V²·f depends entirely on switching frequency f. But every transistor in that block remains powered and continues to leak, so static power stays non-zero unless the supply itself is physically gated off.
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