Which one is "on" at zero gate voltage? The honest answer is: it depends which MOSFET you're holding — and assuming the wrong one is a real design mistake.
Almost every MOSFET most engineers meet — in digital logic, in switching power supplies, in the vast majority of modern ICs — is off with no gate voltage applied, and needs the gate driven past a threshold to switch on. That experience quietly becomes an assumption: "MOSFETs are off until you turn the gate on." It's not universally true. A second, less common family of MOSFET is built to be already conducting the moment it's powered up, with no gate signal at all — and gate voltage is used to turn it more off, not more on. Same three terminals, same basic device physics, opposite default behavior.
The difference comes down to how the device is manufactured, not how it's wired. In an enhancement-mode MOSFET, there is no conducting channel built into the silicon between source and drain — at Vgs = 0 there's simply a gap, and the device conducts nothing. Applying a gate voltage beyond the threshold voltage Vt genuinely creates (enhances) a channel that wasn't there a moment before. In a depletion-mode MOSFET, a thin conducting channel is physically doped into the silicon during fabrication, connecting source to drain before any gate voltage is ever applied — at Vgs = 0 the device is already on. Applying a gate voltage of the appropriate polarity then depletes that pre-existing channel, narrowing it and turning the device progressively more off the further the gate voltage moves from zero.
An enhancement-mode and a depletion-mode MOSFET can share the same package, the same three terminals, and even superficially similar datasheets — but they are different pieces of silicon. In an enhancement-mode device, the region between source and drain is left as ordinary substrate during manufacturing, with no dopant channel connecting them; conduction has to be induced electrostatically, by a gate voltage strong enough to pull enough minority carriers to the surface to form an inversion layer, which only happens once Vgs clears the threshold voltage Vt. In a depletion-mode device, that connecting region is deliberately doped the opposite type from the substrate during fabrication, so a real conducting channel physically exists the instant the device is built — no gate voltage required. Applying a gate voltage of the depleting polarity then pulls carriers out of that pre-built channel (the same electrostatic effect, just working against a channel that already exists rather than building one from nothing), thinning it until, at the pinch-off voltage Vgs(off), the channel is fully depleted and current drops to zero. Same gate electrostatics in both cases — completely different starting point.
That's true for the enhancement-mode devices most engineers work with every day — the switching FETs in a buck converter, the transistors inside a digital logic gate, the vast majority of parts stocked in a typical lab. It is not true in general. Depletion-mode MOSFETs exist specifically because some circuits need a device that is on by default: certain RF amplifier topologies, some current-source and current-limiting designs, and specific normally-on switching applications where the desired failure mode is "stays conducting if the gate drive is lost," not "shuts off." That last point is the practical trap. An enhancement-mode device is fail-safe off if gate drive disappears — the default assumption for most switching designs. A depletion-mode device in the same position is fail-safe on— exactly backward from what the "MOSFETs are off by default" instinct predicts. Someone who assumes a circuit is safely de-energized with no gate signal present, without first confirming which type of device is actually installed, can be dead wrong if a depletion-mode part sits in that position — it would still be happily conducting current.
Explains why some MOSFETs (enhancement-mode) are off by default and need a gate voltage to create a conducting channel, while others (depletion-mode) are built on by default and need a gate voltage to deplete a pre-existing channel — and why assuming every MOSFET follows the enhancement-mode default can lead to real fail-safe design mistakes.
Enhancement-mode MOSFETs dominate modern digital and analog design so thoroughly that "MOSFETs are off until the gate turns them on" becomes an unstated assumption rather than a checked fact. Depletion-mode MOSFETs are far less common in everyday designs but are not exotic or obsolete — they remain the right tool for specific RF, analog, and normally-on applications, and mixing up the two default behaviors is a recurring source of real design errors.
In an enhancement-mode MOSFET, the substrate region between source and drain is left undoped relative to the channel type during fabrication, so no conducting path exists at Vgs = 0; applying a gate voltage beyond the threshold voltage Vt electrostatically induces an inversion layer, creating a channel that did not previously exist. In a depletion-mode MOSFET, a lightly doped channel of the opposite type from the substrate is built in during fabrication, physically connecting source and drain before any gate voltage is applied, so the device conducts at Vgs = 0; applying a gate voltage of the depleting polarity pulls carriers out of that channel, narrowing it until it is fully depleted at the pinch-off voltage Vgs(off), at which point current drops to zero.
The default behavior at zero gate drive is a genuine fail-safe design consideration, not just an academic distinction. Enhancement-mode devices fail safe off if gate drive is lost or a driver circuit fails, which is the default preference for the overwhelming majority of switching applications. Depletion-mode devices fail safe on under the same conditions, which is undesirable in most switching designs but is exactly the behavior wanted in certain normally-on RF stages, some current-source circuits, and specific power applications built around a default-conducting device. Confirming which type is actually installed — rather than assuming the enhancement-mode default — matters whenever "no gate signal" is being relied on as a safe, de-energized state.
Enhancement-mode, by a wide margin. Nearly all digital logic (including every CMOS gate), most switching power supplies, and the vast majority of general-purpose discrete MOSFETs sold today are enhancement-mode devices, precisely because a default-off, gate-activated switch is what most digital and power-switching applications want.
Common uses include certain RF and microwave amplifier stages (where depletion-mode JFETs and MOSFETs have historically offered good high-frequency performance), some current-limiting and current-source circuits that exploit the built-in Idss current at Vgs = 0, and specific normally-on switching or protection circuits where losing gate drive should leave the device conducting rather than shutting it off.
Yes — many depletion-mode devices can be operated with Vgs at, below, or even somewhat above zero, since the physical channel and the gate's electrostatic control both still exist; increasing Vgs beyond zero (in the enhancing direction) can further widen the built-in channel and increase current further, which is why depletion-mode transfer curves are sometimes drawn extending into positive Vgs territory as well as negative.
Check the gate threshold voltage (Vgs(th)) and the zero-gate-voltage drain current (Idss). An enhancement-mode device's datasheet specifies a threshold voltage beyond which the device turns on and typically shows Idss as negligible leakage at Vgs = 0. A depletion-mode device's datasheet specifies a nonzero Idss at Vgs = 0 (a real operating current, not leakage) and a pinch-off/threshold voltage (often called Vgs(off)) at which current drops to zero.
Because it determines what happens during a fault, not during normal operation. If a gate driver fails, a connector comes loose, or a microcontroller resets and stops driving a gate pin, an enhancement-mode MOSFET in that position defaults to off — generally the safer failure mode for a switching load. A depletion-mode MOSFET in the same position defaults to on, continuing to conduct current with no control signal present, which is exactly the wrong assumption to make if the design (or the engineer troubleshooting it) expects an enhancement-mode default.
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