Can an ESD event actually cause latch-up?

Yes — a sufficiently large ESD pulse can inject enough current into the substrate or well to trigger the parasitic PNPN structure into conduction, in addition to (or instead of) causing direct oxide/junction damage. That's exactly why the two failure modes get confused, but the fact that one event can trigger either failure mechanism doesn't make the mechanisms themselves the same thing — one is a sustained regenerative electrical state, the other is instantaneous physical damage.

How is CMOS latch-up actually stopped once it starts?

Removing power (or bringing the supply below the holding voltage of the parasitic thyristor) is the only thing that reliably breaks the positive feedback loop, because both parasitic transistors are actively driving each other's base current — there's no way to interrupt that from outside the loop while power remains applied. This is why latch-up-immune design focuses entirely on prevention (raising the trigger current threshold and lowering parasitic gain) rather than recovery.

What is JEDEC JESD78 and what does it test?

JESD78 is the industry-standard test procedure for CMOS latch-up immunity. It deliberately injects specified overcurrent and overvoltage stress pulses into device pins under defined temperature conditions and checks whether the device latches into a sustained high-current state, separate from and in addition to standard ESD qualification testing (HBM, CDM, and machine model).

Do guard rings stop ESD damage too?

Not directly. Guard rings (rings of substrate or well contacts placed around sensitive circuitry) work by providing a low-resistance path that collects stray injected current before it can raise the local substrate or well voltage enough to turn on the parasitic bipolar transistors — that's a latch-up mitigation. They don't add clamping capability at the I/O pad itself, so a chip still needs dedicated ESD protection cells (diodes, snapback devices) regardless of how good its guard-ring layout is.

Why don't SOI or fully-depleted processes have a latch-up problem?

Silicon-on-insulator (SOI) processes build transistors on a thin silicon layer sitting on an insulating oxide layer, which physically breaks the continuous p-substrate/n-well path that the parasitic vertical and lateral bipolar transistors depend on. Without that continuous doped path between adjacent PMOS and NMOS devices, the PNPN structure that latch-up relies on largely can't form, which is one of the reliability advantages SOI and similar processes offer over bulk CMOS — though ESD protection is still required, since ESD damage doesn't depend on that substrate path at all.

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Latch-Up vs. ESD Damage

Two different ways a CMOS chip can fail — one is a parasitic circuit that gets stuck ON and stays that way, the other is a single transient event that physically damages silicon. They can trigger each other, but they are not the same failure.

Both latch-up and ESD damage get lumped together as "CMOS reliability problems," and both are triggered by the same kind of event — an unexpected voltage or current transient on a pin. But what happens after that trigger is completely different. Latch-up wakes up a parasitic four-layer PNPN structure that every bulk CMOS chip contains whether anyone wants it there or not, and once triggered, that structure locks into a self-sustaining low-impedance short between the supply rails that persists until power is removed. ESD is a single transient discharge event — often nanoseconds to microseconds long — that can punch through gate oxide or blow a junction in that same instant, with no self-sustaining behavior at all. One is a stuck circuit state; the other is one-time physical destruction.