LVDS, DDR, and PCIe signaling standards, differential-pair routing and common-mode rejection, length matching and skew budgets, via stubs and backdrilling, and how SI/PI simulation fits into a real design review.
Module 9 established what a transmission line is, why characteristic impedance matters, and how crosstalk grows with coupled trace length. This module is that same physics taken one level up: how to actually route, budget, and verify a gigabit-class interface — an LVDS link, a DDR memory bus, a PCIe lane — where those fundamentals have to hold true across an entire board at once, not just across one isolated trace. You will work through why differential pairs reject common-mode noise, why DDR's source-synchronous strobe demands a tight, mechanical skew budget while PCIe's embedded-clock recovery trades that requirement for stricter loss and jitter limits, and why an unused via stub that is invisible at low frequency can create a resonant notch right in a multi-GHz signal's operating band.
By the end of this module you should be able to explain why backdrilling becomes necessary on some boards and not others, and where signal-integrity and power-integrity simulation belong in a design review so problems surface while they are still cheap to fix. This module's material is also where the program's hardware gets concrete: Project 3, the High-Speed DDR3 Memory Interface Board in this program's real-project set, is the design where differential routing, length matching, and backdrilling all get applied together on one real layout.