This simulator sends a fixed sequence of block reads through a CPU register, a small direct-mapped cache and RAM. You choose the access pattern and cache size and watch each line fill, hit or evict, while the readouts total the cost in modeled cycles.
• A 3D scene with the CPU request and result register, direct-mapped cache lines, main memory, the read and refill path, and backing storage for context. • An Access trace selector (locality, conflict or stream) and a Cache line count selector (2, 4 or 8). • Readouts for cache hits, cache misses, reads resolved, hit rate, accumulated modeled cycles and mean cycles per resolved read. • Restart demonstration and Advance event buttons, and experiments for locality and conflict thrashing.
A block maps to line (block address mod line count). A read is a hit only if that line is valid and holds the requested block, so matching the index alone does not guarantee a hit; the stored block must match. A hit costs 1 cycle and a miss costs 1 plus a 20-cycle refill. In the locality trace the lab shows three cold misses followed by five hits over the eight reads; in the conflict trace, blocks 0 and 4 map to the same line in a four-line cache and all eight reads miss. Mean cycles per read equals total cycles divided by reads resolved.
The cache holds one block per line, is direct mapped, read-only and starts cold. RAM is treated as resident, so a miss costs a RAM refill rather than disk I/O. Latencies are illustrative. There is no TLB, L2 or L3 cache, writes, coherence or demand paging, and each event takes 0.8 animation seconds.
No. The stored block must also match the requested block. Many blocks map to the same index, which is exactly what the conflict trace exploits.
No. In this lab the blocks are RAM-resident, so a miss is a refill from main memory at 21 modeled cycles, not a storage access.
Two blocks that map to the same line keep evicting each other, so every access finds the wrong block there. Larger caches change the mapping, which you can test with the cache line count selector.
Cache hits divided by reads resolved so far. Together with the mean cycles per read it shows how much locality in the access pattern reduces average latency.