This simulator models a static transfer switch (STS) built from two antiparallel thyristor banks, each fed from an independent AC source, feeding a single-cord IT load through a DC hold-up capacitor. Fail a source, mismatch the phase between sources, and tune the transfer timing to see when the load rides through a transfer and when it resets.
• 01 Facility laboratory tab: a real-time 3D workbench of source A and B terminals, the two antiparallel thyristor banks, the load DC hold-up capacitor and the single-cord load, with Home view, Focus selected part, Show full enclosure, Exploded view, Auto rotate, Expand and Hide/show labels camera controls, clickable numbered components with callouts, live stats, a sequence readout, switch-state tokens and a readings table. Experiment controls include Pause/resume, Advance 10 ms, Advance 1 s, a playback-speed selector (10× slow motion, real time, 10× faster, 1 minute per second), Enable facility / Stop experiment / Open source A / Open source B / Restore sources actions, an IT load slider (10–240 kW), Source A healthy / Source B healthy checkboxes, a source phase difference slider (−180° to 180°), a transfer open interval slider (1–30 ms) and a load supply hold-up slider (0–30 ms). • 02 Curves & measurements tab: a torque/load operating-point chart, a speed-and-current history chart, model equations (the load-reset condition, the transfer-permission condition and the mutual-exclusion rule) and snapshot readouts for source A power, source B power, instantaneous supply gap, longest supply gap, load reset events and conducting power. • 03 Experiments tab: guided presets (fast healthy transfer, hold-up exceeded, phase mismatch, both sources unavailable) plus a Model verification bench ("Run model checks") using independent fresh models, and a timestamped event log with trial-report export. • 04 Learn & assess tab: lessons on mutual exclusion, qualifying the alternate source, the difference between a brief supply gap and an actual IT interruption, and how hold-up time can be exceeded, a two-question knowledge-check quiz with reset, and a scope-and-references note.
An STS keeps two independent AC source banks — antiparallel thyristor stacks in this model — available to a single load, but only ever permits one bank to conduct at a time. Before the incoming bank is enabled, the outgoing bank is blocked, which is why the switch is called break-before-make rather than a true make-before-break transfer: the load briefly loses a conducting source during the modeled transfer open interval.
Before transfer is allowed, the alternate source must also be healthy and within the teaching phase-mismatch window (±15° in this model) — the phase-mismatch experiment shows that even a fully healthy alternate source blocks transfer if it's too far out of phase. Whether that brief gap actually interrupts the IT load depends on the load's own DC hold-up time: the simulator's hold-up capacitor can bridge a gap shorter than its configured hold-up interval, and only records a load reset event the first time a continuous gap exceeds that hold-up time.
The stats panel reports source A and B power, the instantaneous supply gap, the longest supply gap recorded, the count of load reset events, and total conducting power. A transfer that completes within the load's hold-up time produces a nonzero instantaneous gap but zero reset events; a transfer that exceeds hold-up produces exactly one reset event per qualifying gap, which is the key distinction the fast-healthy-transfer and hold-up-exceeded experiment presets are designed to contrast.
The Run model checks button in the Experiments tab exercises the mutual-exclusion, phase-qualification and hold-up logic against independent model instances without disturbing your live trial. This is a discrete source-transfer model: it does not solve an SCR commutation waveform, current-zero detection, or frequency drift — the phase window and transfer/hold-up timings are configurable teaching values, not specific equipment ratings.
Because the outgoing thyristor bank is blocked before the incoming bank is permitted to conduct — the two sources are never deliberately paralleled. This mutual exclusion briefly interrupts the conducting path during the transfer, which is why the transfer open interval and the load's hold-up time both matter.
The alternate source must be within the model's ±15° teaching phase-mismatch window in addition to being healthy. The phase-mismatch experiment preset sets a 60° mismatch to show that transfer is blocked even though the B source itself is otherwise available.
No. The load's own DC hold-up capacitor can bridge a gap shorter than its configured hold-up time without a reset. The simulator only counts a load reset event the first time a continuous gap exceeds the configured hold-up interval — see the fast-healthy-transfer preset (no reset) versus the hold-up-exceeded preset (one reset).
The Run model checks button in the Experiments tab runs automated checks against independent, freshly created model instances, confirming the mutual-exclusion rule, the phase-qualification condition and the hold-up/reset logic behave correctly.