This simulator models a generic three-level radial distribution bench — main breaker, feeder breaker and branch breaker — so you can inject a fault at any level and see which protective devices actually trip, whether healthy loads stay supplied, and how generic time-current curves compare at a given fault current.
• A real-time 3D cutaway of the source transformer/fault-loop equivalent, main breaker, feeder breaker, branch breaker, a movable red fault fixture, a healthy sibling branch load, a separate main-bus panel, and a trip recorder/curve analyzer, with toggleable enclosure, auto-rotate, expand and selectable numbered components with callouts. • A fault-location selector (branch circuit, feeder bus ahead of branch, or main bus ahead of feeder) plus fault-driving source voltage and total fault-loop impedance sliders. • Independently adjustable branch, feeder and main pickup currents, inverse-time coefficients, instantaneous trip multiples (× pickup) and fast-clearing times — nine sliders in total across the three protection levels. • Direct actions: start/stop trial, apply fault, remove fault, and reset-and-reclose breakers. • A Curves & measurements tab with a fault-current chart (branch/feeder/main), a trip-state chart, the model equations, and live readouts including prospective fault current, actual clearing time, the branch–feeder timing-band gap, and whether the healthy sibling and other main-bus panel stayed supplied. • A Test & diagnose Experiments tab with four guided experiments (selective branch clearing, an upstream breaker racing the branch, a feeder-bus fault, a main-bus fault) plus a Verification bench of automated model checks and a timestamped event log with report export. • A Learn & assess tab with four guided lessons, a two-question knowledge-check quiz, and a written model-scope statement with an industry reference link.
Prospective fault current is simply the fault-driving source voltage divided by the total fault-loop impedance (a single-equivalent-voltage calculation, not a full three-phase fault study). Only devices upstream of the selected fault location actually see that current — a branch fault is seen by the branch, feeder and main; a feeder-bus fault bypasses the branch device entirely; a main-bus fault is seen only by the main.
Each device follows a generic definite/inverse curve: above its instantaneous multiple × pickup it clears in a fixed fast-clearing time, otherwise its clearing time follows t = max(fast-clearing time, K / [(I/pickup)² − 1]), where K is that device's inverse-time coefficient. The simulator accumulates progress as dt / t(I) each model step and trips the device once progress reaches 1, so you can watch a race between two devices resolve in real (slowed) time rather than as an instantaneous curve lookup.
The curve view overlays each device's nominal clearing time with an illustrative ±20% tolerance band (0.8t to 1.2t), and the reported branch–feeder margin is computed as 0.8×feeder time − 1.2×branch time — a nominal timing gap alone isn't sufficient evidence of a robust margin once you account for overlapping bands. The trip recorder timestamps the actual order in which devices open so you can directly verify whether the branch cleared first and whether the sibling branch or the other main-bus panel remained supplied.
Per the model's scope statement, these are generic teaching curves with an illustrative tolerance band — not listed manufacturer device curves, code-required settings or certified selectivity tables. The model excludes current limiting, an arc-energy calculation, asymmetrical peak current, full thermal memory and a three-phase network fault study; fast-clearing times are an abstraction of contact-interruption time, and animation is intentionally slowed relative to the underlying 1 ms model substeps.
Only devices upstream of the fault location carry its current, and each follows t = max(fast-clearing time, K/[(I/pickup)²−1]) above pickup, or a fixed fast-clearing time above its instantaneous multiple. Selective clearing means the nearest upstream device reaches trip progress = 1 before any device further upstream, isolating the smallest possible portion of the system.
Real protective devices have manufacturing and operating tolerance around their nominal curve. The simulator overlays an illustrative ±20% band on each device to show that a nominal timing gap between two curves does not guarantee a coordination margin once tolerance is considered — the model computes the branch–feeder margin using the worst-case edges of both bands (0.8×feeder − 1.2×branch).
Yes. A branch fault only removes the faulted branch itself (if coordination holds) while the sibling branch and the other panel stay supplied. A feeder-bus fault removes both branches on that feeder while the other main-bus panel stays up. A main-bus fault removes everything downstream of the main.
It uses generic definite/inverse curves with an illustrative tolerance band, not real manufacturer device curves, code-mandated settings or certified selective-coordination tables. It excludes current limiting, arc-flash energy, asymmetrical peak current, full thermal memory and a three-phase network fault study — treat it as a teaching tool for coordination concepts, not a substitute for an actual coordination study.