What does "tape-out" mean?

Tape-out is the point at which a chip's final, fully verified layout — exported as GDSII files describing every physical layer of the design — is submitted to the semiconductor foundry for mask-making and fabrication. The name is a holdover from when layout data was physically shipped to the foundry on magnetic tape. After tape-out, the design is effectively frozen; any further change requires a costly new mask set and fabrication run.

Why is ASIC verification so expensive and time-consuming?

Because a logic bug that survives verification and reaches silicon cannot be patched the way software can be updated after release. Fixing it typically requires a full mask re-spin costing millions of dollars and months of delay, so teams invest heavily in simulation, constrained-random testing, and formal verification to catch bugs while they are still nearly free to fix. On many projects, verification consumes more engineering effort than the RTL design itself.

What's the difference between RTL design and physical design?

RTL design (the front end) describes the chip's intended behavior in a hardware description language like Verilog or VHDL, at the level of registers and the logic between them, and is verified through simulation. Physical design (the back end) takes the synthesized, verified netlist and turns it into an actual manufacturable layout — floorplanning, placing gates, routing wires, and closing timing — resulting in the GDSII files sent to the foundry.

When does it make financial sense to design an ASIC instead of using an FPGA?

An ASIC becomes worthwhile once production volume is high enough that its lower per-unit cost, lower power consumption, and higher performance outweigh the large upfront non-recurring engineering (NRE) cost, which can run into the tens of millions of dollars for mask sets and tooling at modern process nodes. For low-volume products, or designs likely to change after deployment, an FPGA's reconfigurability and much lower upfront cost usually make more sense, which is why many ASIC designs are prototyped and validated on an FPGA first.

Engineering·8 min read·July 5, 2026

🔬 ASIC Design Flow: From RTL to Silicon

A stage-by-stage technical walkthrough of how an Application-Specific Integrated Circuit moves from a written specification through RTL design, verification, synthesis, physical design, and tape-out, including the NRE economics that decide when an ASIC beats an FPGA.

📖Practical ASIC Design & Implementation — Illustrated Guide (Full Access)

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What Is an ASIC, and Why Build One

An Application-Specific Integrated Circuit (ASIC) is a chip designed and fabricated to do one job, and only that job. Unlike a general-purpose microprocessor or a reconfigurable FPGA, an ASIC has no spare logic, no configuration memory, and no routing flexibility left over after manufacturing. Every transistor on the die is wired to do exactly one thing. That specialization is precisely what makes ASICs attractive at scale: with no reconfigurable overhead to carry around, an ASIC implementation of a given function is smaller, faster, and consumes markedly less power than the same function running on an FPGA's programmable fabric or on a general-purpose processor.

Topics covered

ASIC design flowRTL to GDSIIapplication-specific integrated circuittape-outlogic synthesisplace and routetiming closuredesign rule checklayout versus schematicstandard cell libraryfunctional verificationFPGA vs ASICnon-recurring engineering costfloorplanningGDSIIphysical design