🔢 Digital Logic Design Fundamentals: Combinational and Sequential Circuits

Binary Values and the Basic Logic Gates

All digital logic reduces to two states: 0 and 1, also expressed as LOW and HIGH voltage levels, or false and true. Every digital circuit, no matter how complex, is built from combinations of a small set of logic gates that operate on these binary signals. Understanding what each gate does at the level of its inputs and outputs is the foundation for everything else in digital design.

The AND gate outputs 1 only when all of its inputs are 1; if any input is 0, the output is 0. The OR gate outputs 1 if at least one input is 1, and only outputs 0 when every input is 0. The NOT gate (an inverter) simply flips its single input: a 0 becomes 1, and a 1 becomes 0. The NAND gate is an AND gate followed by a NOT gate, so it outputs 0 only when all inputs are 1, and 1 otherwise. The NOR gate is an OR gate followed by a NOT gate, outputting 1 only when all inputs are 0. The XOR (exclusive OR) gate outputs 1 when its inputs differ (an odd number of 1s among its inputs), and 0 when they match. The XNOR gate is the inverse of XOR, outputting 1 when its inputs are the same.

NAND and NOR each have a special property: they are universal gates. Any other logic gate, and therefore any logic function at all, can be constructed using only NAND gates, or only NOR gates, wired together in different combinations. This matters enormously in real chip fabrication because a manufacturing process optimized to produce one gate type extremely well, and to repeat it millions or billions of times across a die, is far simpler and more reliable than a process that must fabricate many different gate structures. Many standard cell libraries used in real chip design are built primarily from NAND- or NOR-based structures for exactly this reason.

Combinational Logic Circuits

A combinational logic circuit is one whose output depends only on the current values of its inputs. It has no memory of what the inputs were a moment ago. Change an input, and the output changes essentially immediately, limited only by the propagation delay of the gates the signal passes through. There is no clock and no stored state involved.

A classic example is the half adder, which adds two single-bit inputs, A and B, producing two outputs: a sum bit and a carry-out bit. The sum output is simply A XOR B, since the sum of two bits is 1 exactly when the bits differ, and the carry-out is A AND B, since a carry is only generated when both inputs are 1. The half adder cannot accept a carry from a previous bit position, which limits it to single-bit addition.

The full adder extends this by also accepting a carry-in from a previous stage, so it adds three bits total (A, B, and carry-in) and produces a sum and a carry-out. Full adders are chained together, with each stage's carry-out feeding the next stage's carry-in, to build multi-bit adders such as those found in an arithmetic logic unit (ALU) that performs addition on entire binary words.

A multiplexer (MUX) is a combinational circuit that selects one of several data inputs and routes it to a single output, based on the binary value of one or more select lines. For example, a 4-to-1 multiplexer uses two select lines to choose which of four data inputs appears at the output. Multiplexers are used constantly in datapaths to route one of several possible values onto a shared bus or into a functional unit.

A decoder does roughly the reverse job: given a binary input code, it activates exactly one of its many output lines, the one corresponding to that code, while all other outputs stay inactive. Decoders are used for tasks such as selecting one memory chip or one register out of many based on an address.

Sequential Logic Circuits

Unlike combinational logic, a sequential logic circuit has memory. Its output depends not just on the current inputs but on the circuit's stored internal state, which reflects the history of past inputs. Building memory into a circuit requires feedback, where a gate's output is routed back to influence its own future input, and in practical designs it requires a clock signal to control precisely when that stored state is allowed to change.

The simplest memory element is the SR latch (set-reset latch), typically built from two cross-coupled NAND or NOR gates. Asserting the set input forces the stored output to 1, and asserting the reset input forces it to 0; when neither is asserted, the latch holds its previous value. The SR latch's major flaw is that asserting both set and reset simultaneously drives it into an undefined or forbidden state, so it is rarely used directly in real designs.

The D flip-flop is the standard building block of essentially all modern sequential logic. It captures whatever value is present on its D input and holds that value at its output, but it only does so at the moment of a clock edge (typically the rising edge), rather than continuously like a latch. Between clock edges, the D flip-flop's output stays fixed regardless of what the D input does. This edge-triggered behavior is what makes synchronous digital design predictable: a designer can reason about the circuit one clock cycle at a time, since state only changes at well-defined instants.

Chaining flip-flops together builds larger structures. A group of D flip-flops sharing a common clock forms a register, capable of storing a multi-bit value such as a byte or a word. A counter is a register combined with combinational logic that computes the next count value, so that it increments (or decrements) by one on every clock cycle. A finite state machine (FSM) generalizes this further: it is a circuit whose behavior is defined by a fixed set of states, stored in flip-flops, along with combinational logic rules that determine both the outputs and the next state based on the current state and the current inputs. FSMs are the basis of nearly all real control logic, from simple sequence generators to the control units that direct a processor's datapath.

Why the Clock and Synchronous Design Matter

In any real circuit, signals travel through different paths with different numbers of gates and different wire lengths, so they do not all arrive at their destinations at exactly the same instant. If state were allowed to update the moment any signal changed, these differing delays could cause a circuit to briefly evaluate an inconsistent, glitchy combination of signal values, some old and some new, potentially corrupting stored state or producing incorrect outputs.

Synchronous design solves this by having every flip-flop in the system update only on the same shared clock edge, with all combinational logic given the time between clock edges to fully settle before that next edge arrives. This turns an otherwise chaotic web of timing-dependent behavior into something analyzable one clock cycle at a time. It is also precisely why timing analysis is such a central part of real digital design: engineers must verify that combinational logic between two flip-flops finishes settling before the next active clock edge (satisfying setup time) and that flip-flop outputs remain stable long enough after the clock edge for downstream logic to read them correctly (satisfying hold time). A design that violates setup or hold time can behave correctly in simulation yet fail unpredictably on real silicon.

Element Comparison

From Gates to HDL and Synthesis

In modern practice, engineers rarely wire individual gates and flip-flops by hand. Instead, this same logic, adders, multiplexers, registers, FSMs, is described at a higher level of abstraction in a hardware description language (HDL) such as Verilog or VHDL, a topic covered in a companion article. A synthesis tool then automatically translates that description down into the actual gates and flip-flops discussed here, mapped onto a specific target technology such as an FPGA's logic cells or an ASIC's standard cell library.

Even so, understanding these fundamentals remains essential. It is what allows an engineer to read a synthesis report and understand what logic was actually generated, to diagnose why a design reports a timing violation on a particular path, or to trace unexpected behavior in a simulation back to a specific latch, flip-flop, or combinational path. The abstraction that HDLs provide does not remove the underlying gate-level and clock-edge-level reality; it just changes how directly engineers interact with it.