🧩 FPGA Fundamentals: How Field-Programmable Gate Arrays Work

A field-programmable gate array (FPGA) is an integrated circuit built from a large grid of generic, reconfigurable logic elements connected by a programmable wiring fabric. Unlike a microprocessor, which runs software instructions sequentially, or an ASIC, whose transistors are permanently wired for one function during manufacturing, an FPGA has no fixed function at all until it is configured. Load one bitstream and the chip behaves as a UART; erase it and load another, and the exact same silicon becomes a video scaler, a motor controller, or a 256-tap FIR filter. This reconfigurability, done entirely at the hardware level rather than in software running on fixed hardware, is what separates FPGAs from every other class of digital chip.

Inside the Fabric: LUTs, CLBs, and Interconnect

The basic building block of an FPGA is the look-up table (LUT). A LUT is a small block of memory, commonly with 4 to 6 inputs, that stores a truth table rather than implementing logic with dedicated gates. A 4-input LUT has 16 memory cells, one for every possible combination of its four inputs; when synthesis tools decide what Boolean function a piece of your circuit needs, they simply write the correct output value into each of those 16 cells. Because any Boolean function of N inputs can be described by its truth table, a single LUT of the right size can implement literally any function of that many inputs — an AND gate, an XOR gate, a full adder's carry logic, or an arbitrary custom function, all using the identical physical memory structure. This is the core trick that makes an FPGA generic: it doesn't contain millions of different gate types, it contains millions of tiny, identical, rewritable truth tables.

Configurable Logic Blocks (CLBs)

LUTs are grouped, along with flip-flops and multiplexers, into configurable logic blocks (CLBs) (Xilinx terminology; Intel/Altera calls the equivalent unit a logic array block, or LAB). The flip-flops give a CLB the ability to hold state and implement clocked, sequential logic — registers, counters, state machines — not just instantaneous combinational functions. Multiplexers inside the CLB let the tool chain choose whether a LUT's output goes straight out combinationally or gets latched into a flip-flop first, and let adjacent LUTs be chained together to build wider functions or fast carry chains for arithmetic.

Programmable Interconnect

CLBs by themselves are useless without a way to wire them together, and this is the second reconfigurable layer of an FPGA: the programmable interconnect, made up of metal routing tracks and switch boxes at the intersections between them. Each switch box contains programmable pass transistors that can connect an incoming wire to any of several outgoing wires. The place-and-route tool decides, for a given design, exactly which switches get turned on to route a signal from one CLB's output to another CLB's input, possibly hopping through several switch boxes along the way. Around the perimeter of the die sit I/O blocks, which are themselves configurable for voltage standard, drive strength, and direction, connecting the internal fabric to the physical pins of the package.

Hardened Blocks: DSP Slices, BRAM, and Embedded Cores

Building every function purely out of LUTs is flexible but inefficient for operations that are extremely common and performance-critical, particularly multiplication. Modern FPGAs therefore include hardened, non-reconfigurable blocks dropped into the fabric alongside the generic LUT array: DSP slices are dedicated multiply-accumulate units, far faster and denser than an equivalent multiplier built from LUTs, essential for filters, FFTs, and other signal-processing math. Block RAM (BRAM) provides dedicated, fast on-chip memory for buffers, FIFOs, and lookup tables of data (as opposed to lookup tables of logic). Some devices, such as Xilinx's Zynq family or Intel's SoC FPGAs, go further and embed a hardened ARM processor core directly on the same die as the programmable fabric, letting a design run an operating system on the processor side while offloading timing-critical or parallel work to the FPGA fabric side.

The Design Flow: From HDL to Bitstream

Engineers do not draw individual LUT connections by hand. Instead they describe the desired circuit behavior in a hardware description language (HDL), almost always Verilog or VHDL (covered in depth in a companion article on this site). A synthesis tool reads that HDL and translates it into a generic network of logic gates and registers that implements the described behavior. A place-and-route tool then takes that gate network and maps it onto the specific physical LUTs, flip-flops, DSP slices, and routing resources available on the target FPGA part, choosing which physical CLB implements which piece of logic and which switch-box paths carry each signal, all while trying to meet the design's timing requirements. The final output of this flow is a bitstream — a binary file containing the configuration data for every LUT truth table, every routing switch, and every I/O setting on the chip. At power-up, the FPGA loads this bitstream from onboard configuration flash or an external configuration device, and only then does the previously generic silicon become the specific circuit the designer intended.

FPGA vs. CPU vs. ASIC

A CPU executes a stream of instructions sequentially (per core), which makes it extremely flexible and trivial to reprogram — you just change the software — but comparatively slow for tasks that are naturally parallel or that require deterministic, cycle-accurate hardware timing, since instruction fetch, decode, and an operating system's scheduling all introduce variability. An ASIC (Application-Specific Integrated Circuit) sits at the opposite extreme: it is custom-designed and fabricated for one function only, with transistors wired permanently at the mask level. At high volume an ASIC is unbeatable on cost per unit and power efficiency, but non-recurring engineering cost and fabrication lead time are enormous, and a design bug found after chips are back from the foundry generally requires an expensive, months-long re-spin. An FPGA occupies the middle ground: its logic is reconfigurable like software, but because that logic runs as actual parallel hardware rather than sequential instructions, it can achieve much of the speed and determinism of an ASIC while still allowing a bug fix or feature change to be pushed out as a new bitstream, even after the product has shipped.

Where FPGAs Actually Get Used

• High-speed signal processing: radar systems and software-defined radio rely on FPGA DSP slices to perform millions of filter and FFT operations per second in parallel, in hardware, rather than in a software loop.
• Prototyping before an ASIC: teams designing a future ASIC will often first implement and validate the logic on an FPGA, since it lets them test real hardware behavior and fix bugs cheaply before committing to an expensive, unchangeable mask set.
• Video and image processing pipelines: processing every pixel of a high-resolution video stream in real time benefits from the FPGA fabric's ability to run many parallel pixel-processing operations simultaneously rather than one at a time.
• Low-latency financial trading: trading systems use FPGAs to implement order-matching and market-data logic directly in hardware, achieving deterministic, nanosecond-scale latency that a software stack on a CPU cannot guarantee.
• Aerospace and defense: systems that must be reconfigured in the field — to patch a bug, adapt to a new waveform, or add a capability — without swapping physical hardware are a natural fit for FPGAs, since a new mission profile can sometimes be uploaded as simply a new bitstream.

Understanding the LUT-CLB-interconnect architecture, and the honest tradeoffs against CPUs and ASICs, is the foundation for everything else in FPGA design — including the HDL coding practices, timing closure techniques, and toolchain specifics covered in the companion articles on this site.