From Sand to a Perfect Crystal
Every computer chip begins as ordinary silicon dioxide (sand or quartzite). Producers first reduce it in a furnace with carbon to yield metallurgical-grade silicon, which is only about 98-99% pure — far too dirty for electronics. That material is then converted into electronic-grade polysilicon through a purification process (commonly the Siemens process), reaching a staggering purity of 99.9999999% silicon, an industry shorthand known as "nine nines." At that purity, contaminant atoms are rare enough that they won't disrupt the electrical behavior of transistors that are only tens of nanometers across.
Purity alone isn't enough; the atoms also need to line up in a single, defect-free crystal lattice. This is achieved with the Czochralski process: a small seed crystal is dipped into a crucible of molten polysilicon and then slowly pulled upward while both the seed and the crucible rotate. As it's pulled, silicon solidifies onto the seed in the same crystal orientation, growing a cylindrical single-crystal ingot (also called a boule) that can be well over a meter long. This ingot is sliced into thin discs using a wire saw, then lapped, etched, and polished to a mirror finish. The result is a wafer — commonly 200mm (8-inch) or 300mm (12-inch) in diameter today — which serves as the substrate on which chips are built. A single wafer will eventually be diced into hundreds or thousands of individual chips (dies).
Photolithography: Printing Circuits with Light
Photolithography is the step repeated most often in chip fabrication, since it's what defines every pattern on every layer of the chip. The wafer is first coated with a thin, uniform layer of photoresist, a chemical that changes its properties when exposed to light. The wafer is then loaded into a precision optical tool — a stepper or scanner — which projects light through a patterned photomask (or reticle) and a reduction lens onto the resist. Wherever light passes through the mask's pattern, it triggers a chemical reaction in the resist beneath it.
Depending on whether a positive or negative resist is used, either the exposed or the unexposed regions become soluble in a developer solution. The wafer is then developed, washing away the soluble resist and leaving behind a precise stencil that exposes the underlying material in exactly the pattern needed for the next processing step, whether that's etching, doping, or deposition.
The smallest feature a lithography tool can print is fundamentally limited by the wavelength of light used. This is why leading-edge fabs have moved to extreme ultraviolet (EUV) lithography, which uses light with a wavelength of just 13.5 nanometers — dramatically shorter than the 193nm deep-ultraviolet light used at older nodes. Shorter wavelengths allow much finer, denser patterns to be printed in a single exposure, which is essential for building the multi-billion-transistor chips used in modern processors. EUV tools are extraordinarily complex: because no material transmits 13.5nm light efficiently, the entire optical path uses reflective mirrors in a vacuum, and the light itself is generated by vaporizing microscopic droplets of molten tin with a high-power laser, tens of thousands of times per second.
The Core Fabrication Cycle: Etch, Dope, Deposit
Photolithography by itself doesn't change the wafer — it just creates a stencil. The actual chip structure is built through three other repeated processes, applied in sequence with lithography, layer after layer.
Etching
Etching removes material that isn't protected by the patterned resist. Wet chemical etching uses liquid acids or bases and is simple but tends to etch in all directions somewhat equally, limiting precision. Most advanced fabrication instead uses plasma (dry) etching, where a chemically reactive, electrically charged gas bombards the wafer and removes material with much finer directional control, which is necessary for the extremely narrow, high-aspect-ratio features used in modern transistors.
Doping (Ion Implantation)
Silicon on its own is a poor conductor. To create functioning transistors, engineers introduce controlled amounts of impurity atoms — most commonly boron (which creates "p-type" silicon with a shortage of free electrons) or phosphorus and arsenic (which create "n-type" silicon with an excess of free electrons). This is done through ion implantation, where dopant atoms are ionized, accelerated to high energy, and fired directly into specific, precisely defined regions of the wafer exposed by the lithography step. The junctions formed between adjacent p-type and n-type regions are what allow a transistor to switch on and off.
Thin-Film Deposition
Deposition adds new layers of material on top of the wafer — insulating oxides, polysilicon, or metal for wiring. This is done using chemical vapor deposition (CVD), where gaseous precursors react at the wafer surface to leave behind a solid film, or physical vapor deposition (PVD), such as sputtering, where atoms are physically knocked off a solid source material and land on the wafer.
A modern logic chip requires this lithography → etch → dope → deposit cycle repeated dozens to hundreds of times, alternating between building individual transistors near the wafer surface and then stacking many layers of metal interconnect wiring above them to connect billions of transistors together.
What a "Process Node" Actually Means Today
Older process node names — like 350nm, 130nm, or 90nm — corresponded reasonably closely to an actual physical dimension, typically the transistor's gate length. That correspondence has broken down. At nodes like "7nm," "5nm," and "3nm," the number is best understood as a generational marketing label rather than a literal measurement of any single transistor feature. Different foundries define their node names using different internal metrics, so a TSMC "5nm" process, a Samsung "5nm" process, and an Intel process with a different naming scheme are not directly comparable by their labels alone.
| What people assume | What's actually true |
|---|---|
| The node number is a physical transistor dimension | It's a marketing/generational name; no single 5nm-scale feature necessarily measures 5nm |
| Node names are comparable across foundries | TSMC, Samsung, and Intel each use different internal definitions |
| A smaller number always means a better chip | Actual performance depends on transistor density, switching speed, and power draw, measured directly |
What matters in practice is the measurable generation-over-generation improvement in transistor density (transistors per square millimeter), switching speed, and power consumption — the actual engineering gains a node delivers, rather than the number in its name.
Testing, Dicing, and Packaging
Once fabrication of a wafer is complete, it undergoes wafer probe (wafer sort): an automated tester touches tiny electrical probes to each die on the wafer while it's still whole, running functional tests to flag which dies are good and which are defective, before any cutting happens. Manufacturing at this scale is never perfect — some fraction of dies on every wafer will fail, and yield (the percentage of good dies) is one of the most closely watched metrics in the industry.
The wafer is then diced, cutting it into individual chips. Good dies move on to packaging, where the bare silicon die is mounted into a protective package that also provides electrical connections to a circuit board — either via wire bonding (fine gold or copper wires connecting pads on the die to the package leads) or flip-chip mounting (the die is flipped over and connected directly through an array of solder bumps, allowing many more connections in less space). After packaging, chips go through final test to confirm they meet performance and reliability specifications before shipping to customers.
Why Leading-Edge Fabs Cost $15-20 Billion
A single EUV lithography machine, made only by the Dutch company ASML, costs on the order of $150-400 million, and a leading-edge fab needs dozens of them alongside hundreds of other specialized tools for etching, deposition, ion implantation, and metrology. Add in the ultra-clean cleanroom facilities (air far cleaner than a hospital operating room), enormous water and power demands, and years of process development, and total cost for a single advanced fab commonly reaches $15-20 billion or more.
That level of capital investment, combined with the deep, cumulative process expertise needed to run it profitably, is why only a small handful of companies — TSMC, Samsung, and Intel, along with a few others operating at less advanced nodes — build and operate leading-edge fabs at all. Because owning a fab is so expensive and risky, most chip companies today are fabless: they design chips in-house but pay a dedicated foundry like TSMC to actually manufacture them. This split between chip design and chip manufacturing has become the dominant business model of the modern semiconductor industry.