This simulator puts an eight-bit register on a bench and shows exactly how a pattern of bits is interpreted and added. You choose register A and addend B, then step through place-value contributions, the carry chain and the flag lamps to see why the same bits can mean different numbers.
• A 3D bench with an eight-bit register, place-value contributions, a ripple carry chain and result and flag lamps, each selectable for an explanation. • Two sliders, Register A and Addend B, each from 0 to 255, with Restart demonstration and Advance event buttons. • Six readouts: A interpreted unsigned, A in two's complement, the 8-bit sum, unsigned carry out, signed overflow and the number of set bits in A. • Two experiments that load the classic cases — unsigned wrap and signed overflow.
The unsigned value of a pattern is the sum of each bit times its power of two. The two's complement reading subtracts 256 whenever bit 7 is set, so 11111111 is 255 unsigned but −1 signed. The result is (A + B) mod 256. Carry means the true sum exceeded 255; signed overflow means both operands had the same sign and the result has the opposite one. They are different conditions: 255 + 1 produces a carry but no signed overflow, while 127 + 1 produces signed overflow with no carry — the result 128 then represents −128.
Words are fixed at eight bits. Two's complement is an interpretation of a bit pattern, not a different stored value, and this is not floating-point arithmetic. The carry scan is explanatory rather than a transistor-delay simulation, each event lasts 0.8 animation seconds, and the visual distances are illustrative.
No. Carry concerns the unsigned interpretation; signed overflow concerns the two's complement interpretation. 255 + 1 has a carry out but no signed overflow, which the unsigned wrap experiment shows.
It represents −1. The same eight bits read as unsigned are 255; the lab displays both interpretations side by side for register A.
As (A + B) mod 256. Anything above 255 wraps, and the carry-out lamp records that the wrap happened.
It is the sequence of carries passing from bit 0 up to bit 7 during addition. The lab steps through it so you can see where a carry starts and how it propagates, though it is explanatory and not a gate-delay model.