This simulator walks a tiny accumulator machine through its instruction cycle. The program counter addresses an instruction, the decoder interprets it, and only the execute step changes machine state. You choose the starting data and the immediate value and step one event at a time.
• A 3D processor with a program counter, instruction and data stores, an instruction decoder, an arithmetic logic unit, a control sequencer and an accumulator register. • Two sliders: Initial memory[0] and the ADD immediate value, each from 0 to 255. • Readouts for the next instruction address, the accumulator, data memory[1], instructions completed, the current phase (fetch, decode or execute) and the ALU carry. • Restart demonstration and Advance event buttons, and experiments for addition and store and for overflow at eight bits.
LOAD copies memory[0] into the accumulator. ADD adds an immediate value to it modulo 256. STORE writes the accumulator to memory[1]. HALT stops execution. Each instruction passes through fetch, decode and execute; decoding ADD does not change the accumulator — the state change occurs at the execute event. With memory[0] and the immediate set so the sum exceeds 255, the accumulator and memory[1] hold the wrapped value and the carry lamp shows a carry. The program counter and accumulator are kept distinct on purpose: one addresses instructions, the other holds arithmetic data.
This is a specified educational accumulator instruction set, not an emulator of ARM or x86. It has no pipeline, interrupts, caches or speculative execution, and instruction and data banks are separate as a visual choice. For pipelining, forwarding and caches, use the CPU Architecture Lab, which models a five-stage core. Each event lasts 0.8 animation seconds.
No. Decoding only identifies the operation. The accumulator changes at the execute event, which is why the phase readout distinguishes decode from execute.
They hold different machine state. The program counter addresses instructions, while the accumulator holds arithmetic data being processed.
The ALU result wraps modulo 256 and the carry flag is set. The overflow experiment shows the accumulator and memory[1] holding 4 with carry 1.
No. This lab isolates the basic fetch, decode and execute cycle of a tiny accumulator machine, while the CPU Architecture Lab simulates a five-stage pipelined core with forwarding and a data cache.