This simulator follows a single digital signal from a 24 V PNP field switch on a training conveyor, through input terminal conditioning and qualification, into a PLC's cyclic read/execute/write scan, and back out through a transistor output module to a solenoid valve that strokes a pneumatic cylinder. Adjust the field supply, debounce time, scan interval and injected I/O faults, then watch where the requested behavior and the physical response diverge.
• A real-time 3D cutaway workbench of the conveyor/switch, input module, CPU, output module, 24 V DC supply and solenoid/cylinder, with home view, focus-selected-part, toggleable full-enclosure cutaway, exploded view, auto-rotate and expand controls, tappable numbered components with callouts matching a companion diagram, and a show/hide labels toggle. • Nine live controls: field switch active, logic enable, invert input in logic, CPU in RUN, load supply available, field supply voltage (0–30 V), input qualification (debounce) time, full scan interval, and a fault selector (healthy, input conductor open, load conductor open, input stuck high). • Play/pause, single-step (0.1 s) and larger-step (1 s) time controls, plus a playback-speed selector (10× slow motion, real time, 10× faster, 1 minute per second). • Start trial and Stop trial actions, with a live sequence narrative, switch-state tokens (trial running/stopped, trip/diagnostic status) and per-component status. • Eight live metrics: input terminal voltage, qualified (filtered) input, input image register I0.0, program logic result, output command Q0.0, solenoid coil voltage, coil current and cylinder extension percentage. • A Curves & measurements tab with two charts (filtered input/input image/output vs. time, and coil voltage/cylinder travel vs. time), the full model equations, and snapshot measurements. • An Experiments tab with four guided scenarios (signal chain, missing output power, open input wire, CPU stop), a model-verification bench of independent automated checks, and a timestamped event log with a copyable trial report. • A Learn & assess tab with four guided lessons, a two-question knowledge-check quiz, and a written scope/reference statement.
The model treats voltage hysteresis, the qualified (debounced) input, the PLC's input image register, the logic result and the output command as five separate states that do not necessarily change in step. A raw input is read high above 15 V and low below 5 V, holding its previous state in between; that raw value must then persist for the configured qualification time before it updates the filtered input. The scan cycle itself splits into three equal phases — read inputs, execute logic, write outputs — so the input image can lag the true terminal voltage until its read phase arrives.
Even once Q0.0 is true, the simulator can show zero coil voltage if load supply power is missing or the load conductor is open, or force the output off entirely if the CPU is stopped or the input conductor is open. This is the central diagnostic lesson: a lit output bit is a logic statement, not proof that current is flowing to the field device.
The equations panel states the raw input threshold rule, the three-phase scan sequence, the logic relationship Q = permit AND selected input (with an optional invert), and Icoil = Vcoil / 120 Ω for the fixed coil resistance. The four injectable faults — input conductor open, load conductor open, input stuck high, and a load-supply-missing toggle — each break a different link in that chain so you can practice isolating where a discrepancy originates.
This is a generic educational fixture, not a manufacturer-specific implementation: it models cyclic I/O with configurable scan and qualification times rather than immediate I/O or asynchronous fieldbus updates, uses a fixed coil resistance rather than real transistor output protection, and approximates the pneumatic cylinder's stroke with a fixed travel rate rather than solving actual air-flow dynamics.
The raw input follows voltage hysteresis (high above 15 V, low below 5 V, holding its prior state between them), but it must remain stable for the configured input qualification (debounce) time before the filtered input updates. A pulse shorter than that qualification time never reaches the filtered state, which is exactly what the "short pulse fails qualification" behavior in the model checks demonstrates.
Yes. Q0.0 reflects the program logic result, but the simulator separately models whether load supply power is available and whether the load conductor is intact. Turning off "Load supply available" produces exactly this state — a true output command with zero coil voltage — which is the missing-output-power experiment built into the Experiments tab.
Each configured scan interval is divided into three equal phases: read inputs (updates the input image from the qualified input), execute logic (computes the output image from the input image and the enable/invert settings), and write outputs (updates Q0.0 from the output image). Because these phases are sequential, the input image and the physical terminal voltage are not always equal at a given instant — only after the read phase catches up.
It is a representative educational fixture with generic parameters, not a manufacturer-specific PLC implementation. It models cyclic scan-based I/O rather than immediate I/O or asynchronous fieldbus updates, does not model real transistor output protection circuitry, and approximates pneumatic cylinder motion with a fixed travel-rate rather than solving actual air-supply dynamics.