From silicon boule to finished wafer: crystal growth, photolithography at the limits of light, doping, thin-film deposition and etch, what a process node actually means today, and how yield mathematically drives cost per die.
Every chip this program touches begins as a single-crystal silicon boule pulled from molten silicon, sliced into wafers, and built up layer by layer through a repeating cycle of lithography, doping, deposition, and etch. This module walks that full fab flow end to end: how a Czochralski-grown boule becomes a mirror-polished wafer, why the industry is pushing from deep-ultraviolet lithography toward extreme ultraviolet at advanced nodes, how ion implantation and thermal diffusion each introduce dopant atoms with very different trade-offs, and why copper interconnect uses an inverted damascene process instead of a direct etch.
By the end of this module you should be able to explain why a “7nm” process node no longer refers to any single physical dimension, and why yield falls off exponentially rather than linearly as die area grows — the exact economics behind why large designs increasingly split into smaller chiplets. This module also closes the loop between Module 1's semiconductor physics and Module 6's ASIC tape-out, treating fabrication as the physical execution of both.