Cross-couple two NOR gates — feed each gate's output back into the other's input — and the resulting circuit keeps whatever state it was last set to, even after the triggering input goes away. That's memory, built from pure logic.
Digital logic builds all digital computation from a small set of basic gates (AND, OR, NOT, NAND, NOR, XOR) that implement Boolean logic in hardware. Combinational logic (gates alone) has no memory — output depends only on current input. Sequential logic introduces feedback, and the simplest possible feedback circuit, the SR latch built from two cross-coupled NOR gates, is where memory itself first appears in digital systems.
Feeding each NOR gate's output back into the other gate's input creates a circuit with two stable states — Q=1/Q'=0 or Q=0/Q'=1 — and critically, once either state is reached, the circuit holds it indefinitely with no S or R input applied, because each gate's output is continuously reinforcing the condition that keeps the other gate's output the same. This self-sustaining loop is the fundamental mechanism of digital memory.
The basic SR latch shown here is level-sensitive — sensitive to S/R at any time they're active. Adding a clock input creates a clocked latch, sensitive only during a specific clock phase; further refinement produces edge-triggered flip-flops (D flip-flops, JK flip-flops), which change state only at a clock edge. Chaining flip-flops together builds registers, counters, and ultimately all digital memory and sequential logic — every one traces back to this same cross-coupled feedback principle.
Every register in a CPU, every bit of SRAM, every state machine controlling a PLC or embedded system relies on this exact bistable feedback mechanism (in more refined forms) to hold state between clock cycles. Understanding the SR latch is understanding the actual physical origin of 'memory' in a system built entirely from combinational logic gates that, alone, have none.
In a basic cross-coupled NOR SR latch, asserting both S and R simultaneously forces both outputs to an invalid state (both 0, violating the Q/Q' complementary relationship), and the resulting state when both are released is unpredictable (a race condition) — this is why the S=R=1 condition is normally treated as forbidden/undefined in SR latch design.
A latch is level-sensitive — it responds to its control inputs continuously whenever enabled. A flip-flop is edge-triggered — it only samples and updates its state at a specific clock edge (rising or falling), which makes flip-flops far more predictable to use in synchronous digital systems clocked at a fixed rate.
Yes — a microcontroller's registers and internal state are ultimately built from arrays of flip-flops (typically D flip-flops), each individually storing one bit using the same underlying bistable feedback principle demonstrated by the simple SR latch here, just packaged with clocking and additional control logic.
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