This simulator models a common-emitter amplifier: a loaded voltage-divider bias network sets the transistor's DC operating point, an emitter resistor (with a switchable ideal AC bypass) provides degeneration, and a signal generator drives the base through a coupling capacitor while the collector produces an inverted, amplified output. Adjust supply voltage, bias resistors, collector and emitter resistors, transistor beta, signal amplitude and frequency, then watch the DC bias, gain and clipping behavior respond.
• A real-time 3D cutaway workbench of the signal generator/coupling capacitor, loaded bias divider, transistor package, collector load, emitter resistor/bypass capacitor and dual-trace oscilloscope, with home view, focus-selected-part, toggleable full enclosure, exploded view, auto-rotate and expand controls, tappable numbered components with callouts matching the diagram reference, and a labels toggle. • Nine live controls: collector supply voltage, upper and lower bias resistors, collector resistor, emitter resistor, transistor beta, generator peak amplitude, signal frequency, and an ideal AC bypass checkbox for the emitter resistor. • Play/pause, single-step (0.1 s) and larger-step (1 s) time controls, plus a playback-speed selector from 100x slow motion to 1 minute per second. • A Reset laboratory action that starts a fresh trial, and a live "what is happening" sequence narrative with component status tokens and a readings table. • Ten live metrics: generator waveform, loaded base AC signal, full collector voltage (including DC), collector departure from bias, quiescent collector voltage, quiescent emitter voltage, quiescent collector current, small-signal source-to-collector gain, modeled swing headroom, and instantaneous clipping flag. • A Curves & measurements tab with two oscilloscope-style charts (input vs. collector AC; full collector voltage vs. DC bias), the complete model equation set, and snapshot measurements. • An Experiments tab with four guided scenarios (degenerated amplifier, AC bypass, overdrive/clipping, bias cutoff), a model-verification bench of independent automated checks, and a timestamped event log with a copyable trial report. • A Learn & assess tab with guided lessons (solve DC first, linearize around bias, observe inversion, overdrive the stage), a knowledge-check quiz with reset, and a written scope/reference statement.
The two bias resistors form a loaded Thevenin source (Vth, Rth) that, together with the emitter resistor and beta, sets the quiescent base and collector currents: IBQ = max(0, (Vth − 0.7)/(Rth + (β+1)RE)), with ICQ following from beta and a saturation envelope, and VCQ = Vs − ICQ·RC. This DC operating point determines how much room the collector voltage has to swing before it clips against the supply rail or the emitter voltage floor.
Small-signal gain depends on the intrinsic emitter resistance re = 26 mV/IEQ combined with any unbypassed emitter resistance: Av(base) ≈ −RC/(re + unbypassed RE). Leaving the emitter resistor unbypassed reduces gain but stabilizes it against transistor variation; switching in the ideal AC bypass removes that degeneration and sharply increases gain magnitude, which also makes clipping more likely at the same input amplitude.
Because the collector resistor drop increases with collector current, a larger positive base-driven current produces a lower collector voltage — the classic common-emitter inversion. The generator's 600 Ω source resistance loads the driven base along with the divider, and the collector waveform is limited in this model to the range from VEQ + 0.2 V up to the supply voltage Vs, producing visible clipping when the requested output swing exceeds the available headroom.
This is a midband small-signal model around a piecewise DC solution with illustrative hard clipping: there is no frequency rolloff, no full nonlinear transistor transient, and the emitter voltage is held at its DC bias point for clipping-limit purposes, so large-signal results are qualitative. Component changes are treated as new design experiments at the retained state rather than a model of physically swapping energized parts; use Reset laboratory to start a fresh trial.
A larger base-driven collector current produces a larger voltage drop across the collector resistor. With a fixed supply voltage, that leaves a lower collector voltage — so a rising base signal produces a falling collector voltage, and vice versa.
Selecting the ideal AC bypass removes the emitter resistor from the small-signal (AC) gain equation while keeping it in the DC bias calculation. This sharply raises gain magnitude compared to the unbypassed case, but it also reduces the headroom before the output clips at a given input amplitude.
Setting the upper bias resistor very high and the lower one very low starves the divider Thevenin voltage below the transistor's 0.7 V turn-on threshold, so essentially no base current — and therefore no collector current or usable small-signal gain — is established.
It is a midband, piecewise-DC small-signal model with ideal coupling and bypass elements and hard clipping limits. It does not model frequency-dependent gain rolloff, full nonlinear large-signal transistor behavior, or realistic capacitor charging transients — the emitter node is held at its DC bias value for clipping calculations.