This simulator separates an integrated circuit into its layers so you can see how a signal gets from a device to a receiver: through contacts, Metal 1, vias, Metal 2 and Metal 3, all under passivation. Adjust the route and metal geometry to see resistance, capacitance and delay change, or inject an open via to break the net.
• An exploded stack with a device layer, device contacts, Metal 1 local routing, Metal 2 and Metal 3 routing, vertical interlevel vias, dielectric and passivation, plus a receiver with an RC output indicator. • Controls for exploded layer spacing, total route length (20-2000 µm), metal width (0.2-5 µm), metal thickness (0.2-2 µm), receiver load capacitance (1-50 fF) and an open-via fault. • Readouts for route resistance, line capacitance, lumped RC 50% rise delay, a distributed-line Elmore estimate, receiver voltage and end-to-end continuity. • Experiments for an open via (continuity fails and the receiver is held low) and for widening the route, which halves resistance but raises capacitance.
Line resistance is R = ρCu L/(w t) with ρCu = 2.2×10⁻⁸ Ω·m. Capacitance is approximated by a parallel plate, Cline ≈ εr ε0 w L/d, with εr = 3.9 and d = 0.3 µm. The lumped time constant is τ = R(Cline + Cload), the 50% delay is t50 = ln(2) τ, and the Elmore estimate for a distributed line is about 0.69 R(Cline/2 + Cload). Widening a wire lowers R but raises C, so delay does not necessarily halve; lengthening it raises both, so distributed delay grows roughly with the square of length.
The stack is a three-level conceptual interconnect, not a specific production technology. Resistance omits vias and size-dependent effects, and capacitance uses a parallel-plate approximation. The animation maps each half-cycle to ten RC time constants, and the open-via fault assumes a receiver pull-down.
Many layers let signals cross over each other and be routed densely, with lower layers for short local connections and upper layers for longer, lower-resistance routes. Vias connect the layers vertically.
A wire has resistance and capacitance, so it charges like an RC circuit. The time to reach 50% of the final voltage is about ln(2) times R times the total capacitance in the lumped model.
A wider wire lowers resistance but adds capacitance to neighboring layers. Because delay depends on the product of R and C, the net improvement is less than the resistance change alone.
It breaks the electrical path between layers, so continuity fails and the receiver stays low under the lab's pull-down assumption. It illustrates how one failed via can open an entire net.