This simulator builds one planar nMOS transistor step by step. Reveal each process layer from the bare substrate through isolation, gate oxide, gate patterning, ion implant, anneal, contacts and first metal, and see how implant dose, depth and oxide thickness translate into sheet resistance and gate capacitance.
• A 3D build of the silicon substrate and active area, isolation dielectric, gate oxide and patterned gate, ion implant beam and doped regions, an anneal stage, contact plugs and first metal interconnect. • A process-stage slider (substrate, isolation, oxide, gate, implant, anneal, contacts, metal) and an automatic run option. • Controls for implant sheet-dose exponent (10¹² to 10¹⁴ cm⁻²), uniform implant depth (0.05-0.3 µm) and gate oxide thickness (10-50 nm). • Readouts for the current step, box-profile implanted density, activated sheet concentration, estimated n+ sheet resistance and gate capacitance for a 10 µm² area.
The box-profile density is Nbox = dose / depth. Annealing activates 90% of the dose, giving the activated sheet density, and the sheet resistance is Rsheet = 1/(q μn Nsheet) with μn = 100 cm²/(V·s). Gate capacitance is Cgate = εox A / tox for A = 10 µm², so doubling the oxide thickness halves the capacitance. The follow-the-sequence experiment ends with an activated sheet dose of 9×10¹² cm⁻² and a sheet resistance near 6935 Ω/□.
The flow is an illustrative historical planar nMOS process, not a modern FinFET or gate-all-around recipe, and the steps are condensed. The implant profile is uniform, activation is fixed and mobility is fixed; diffusion, damage, thermal budget and process tolerances are not solved, and dimensions are enlarged.
Ion implantation damages the crystal and leaves many dopants inactive. Annealing repairs the lattice and activates dopants so they contribute carriers. The lab assumes 90% activation.
Sheet resistance falls as the activated sheet density rises, following Rsheet = 1/(q μn Nsheet). Doubling the dose roughly halves the resistance in this model.
Gate capacitance is εox A / tox, so it is inversely proportional to oxide thickness. Doubling tox halves the capacitance for the same gate area.
Only conceptually. Modern processes use FinFET or gate-all-around devices, many more steps and far tighter control. This lab shows the basic planar sequence.