Why the presence of memory — not the complexity of the gates — is the entire dividing line between a circuit that computes and a circuit that remembers.
A student staring at a schematic full of AND, OR, and XOR gates often assumes any circuit built from "plain logic gates" must be combinational, and anything with a clock symbol must be sequential. Both guesses miss the actual test. The real question is narrower and much more mechanical: does the circuit's output depend only on the present inputs, or does it also depend on what happened before — a stored state the circuit remembers from a previous moment in time? A full adder built from nothing but gates is combinational. A single JK flip-flop, which is also built from gates (cross-coupled NAND or NOR gates, specifically), is sequential — because it has feedback that lets its output depend on its own history, not just its current inputs.
Look at the sequential diagram closely: the "next-state logic" block is itself just a combinational network of gates — no different in kind from the full adder. What turns the whole circuit sequential is that its output, Q, is looped back and used as one of the inputs to that same combinational block. That loop is what a bistable storage element (a latch or flip-flop) creates: a path where the present output becomes part of the next computation. Formally, this is the Moore/Mealy finite-state-machine model taught in every digital-design course — next state = f(inputs, current state), and in a Mealy machine the output can additionally depend directly on the inputs, not just the state. Remove the feedback loop and the flip-flop, and you are left with a purely combinational block again. That is why gate count or apparent circuit complexity is never the right signal — a giant multiplexer tree is still combinational, and a single cross-coupled NAND latch is already sequential.
Close, but the clock is a symptom, not the cause. An asynchronous SR latch built from two cross-coupled NOR gates is fully sequential — it stores one bit of state indefinitely — and it has no clock input at all; it changes state purely from the level of its inputs. Conversely, in an HDL like Verilog or VHDL, writing always @(*) inside a clocked module still describes purely combinational logic (a mux, an ALU, decode logic) — the presence of a clock signal somewhere in the filesays nothing about whether that particular always-block infers storage. The only reliable test is the one above: does the block's own output feed back into its own inputs, directly or through a register, such that the same present input can yield a different output depending on prior history? If yes, it is sequential — synchronous (clocked, edge-triggered flip-flops) or asynchronous (level-sensitive latches) — and if no, it is combinational, no matter how many gates, muxes, or decoders are stacked inside it.
Explains the real distinguishing feature between combinational and sequential digital logic — not the number of gates or the presence of a clock signal, but whether the circuit's output depends only on its present inputs or also on stored state fed back from the past — using a side-by-side comparison of a full adder (combinational) and a D flip-flop with next-state feedback (sequential).
Students frequently use "has a clock" as a shortcut for "sequential" and "just gates" as a shortcut for "combinational." Neither holds up: an asynchronous SR or D latch is sequential (it stores state) with no clock input at all, and a combinational always-block in Verilog or VHDL can appear inside a fully clocked module without inferring any storage. The property that actually matters is whether the circuit's current output can depend on something other than its current inputs — specifically, on a previously stored value. Gate count, apparent complexity, and the presence of a clock signal somewhere in the design are all correlated with the answer, but none of them are the definition.
A combinational circuit implements a pure Boolean function: output = f(inputs), evaluated fresh every time, with no memory of any previous input or output. Given the same inputs, it always produces the same outputs, and — ignoring gate propagation delay — it responds essentially immediately to any input change. Full adders, multiplexers, decoders, encoders, comparators, and ALUs are canonical combinational blocks.
A sequential circuit adds a storage element (a latch or flip-flop) whose output is fed back, directly or through additional combinational logic, into its own next-state computation: next state = f(inputs, current state). Because current state persists from the previous clock edge (synchronous) or the previous stable input level (asynchronous), the same present input can produce different outputs depending on that stored history. Registers, counters, shift registers, and finite-state machines are canonical sequential blocks.
This distinction is the backbone of synthesizable RTL design in Verilog and VHDL. A synchronous design partitions logic cleanly into combinational blocks (next-state and output logic, described with blocking assignments and always @(*) or a VHDL process with a full sensitivity list) and sequential blocks (registers, described with non-blocking assignments clocked on a single edge, always @(posedge clk)). Mixing these carelessly — accidentally inferring a latch from an incomplete combinational if/case statement, or building a combinational feedback loop with no register in it — is one of the most common sources of synthesis warnings, simulation/synthesis mismatches, and timing closure failures in real FPGA and ASIC projects. Static timing analysis, setup/hold checking, and clock-domain-crossing analysis all fundamentally depend on correctly identifying which paths are purely combinational (bounded by two registers) and which paths themselves contain a storage element.
Combinational. A mux's output depends only on its current select and data inputs — it has no memory of previous selections and produces the same output instantly (aside from gate delay) for the same input combination.
Yes — this is in fact the normal case for any real digital system. A typical synchronous design is a network of combinational logic blocks feeding into and out of registers (flip-flops); the overall system is sequential because it contains state, but individual sub-blocks within it, like an adder or a decoder feeding a register's D input, are purely combinational on their own.
Yes, if it has a storage element. An SR latch built from cross-coupled NAND or NOR gates has no clock input at all, yet it is sequential — it stores one bit of state and its output depends on the history of its inputs, not just their present values. "Sequential" refers to the presence of memory/state, not to synchronization by a clock; synchronous vs asynchronous is a separate axis describing whether that state changes on a clock edge or on any input change.
If a combinational always @(*) block does not assign every output on every possible path through an if/else or case statement, the synthesis tool must infer a storage element to hold the output's previous value on the unhandled paths — turning what was intended as combinational logic into an unintended latch. This is a frequent, hard-to-spot RTL bug, which is why linting tools flag incomplete case statements and missing else branches, and why "always assign a default value at the top of the block" is a standard defensive coding practice.
Both are sequential (they store state), but a latch is level-sensitive — transparent and passing its input straight through to its output whenever its enable/clock input is active — while a flip-flop is edge-triggered, sampling its input only at the rising or falling edge of a clock and holding that value otherwise. Synchronous digital design overwhelmingly uses edge-triggered flip-flops for registers precisely because their behavior is unambiguous at a single instant in time, which is what makes static timing analysis with well-defined setup/hold windows possible.
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