Is a multiplexer combinational or sequential?

Combinational. A mux's output depends only on its current select and data inputs — it has no memory of previous selections and produces the same output instantly (aside from gate delay) for the same input combination.

Can a circuit be part combinational and part sequential?

Yes — this is in fact the normal case for any real digital system. A typical synchronous design is a network of combinational logic blocks feeding into and out of registers (flip-flops); the overall system is sequential because it contains state, but individual sub-blocks within it, like an adder or a decoder feeding a register's D input, are purely combinational on their own.

Does an asynchronous circuit with no clock count as sequential?

Yes, if it has a storage element. An SR latch built from cross-coupled NAND or NOR gates has no clock input at all, yet it is sequential — it stores one bit of state and its output depends on the history of its inputs, not just their present values. "Sequential" refers to the presence of memory/state, not to synchronization by a clock; synchronous vs asynchronous is a separate axis describing whether that state changes on a clock edge or on any input change.

Why do combinational always-blocks sometimes accidentally infer a latch in Verilog?

If a combinational always @(*) block does not assign every output on every possible path through an if/else or case statement, the synthesis tool must infer a storage element to hold the output's previous value on the unhandled paths — turning what was intended as combinational logic into an unintended latch. This is a frequent, hard-to-spot RTL bug, which is why linting tools flag incomplete case statements and missing else branches, and why "always assign a default value at the top of the block" is a standard defensive coding practice.

What is the difference between a latch and a flip-flop?

Both are sequential (they store state), but a latch is level-sensitive — transparent and passing its input straight through to its output whenever its enable/clock input is active — while a flip-flop is edge-triggered, sampling its input only at the rising or falling edge of a clock and holding that value otherwise. Synchronous digital design overwhelmingly uses edge-triggered flip-flops for registers precisely because their behavior is unambiguous at a single instant in time, which is what makes static timing analysis with well-defined setup/hold windows possible.

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Combinational vs Sequential Logic

Why the presence of memory — not the complexity of the gates — is the entire dividing line between a circuit that computes and a circuit that remembers.

A student staring at a schematic full of AND, OR, and XOR gates often assumes any circuit built from "plain logic gates" must be combinational, and anything with a clock symbol must be sequential. Both guesses miss the actual test. The real question is narrower and much more mechanical: does the circuit's output depend only on the present inputs, or does it also depend on what happened before — a stored state the circuit remembers from a previous moment in time? A full adder built from nothing but gates is combinational. A single JK flip-flop, which is also built from gates (cross-coupled NAND or NOR gates, specifically), is sequential — because it has feedback that lets its output depend on its own history, not just its current inputs.