HDL Syntax Reference

Verilog vs VHDL Syntax Reference

Side-by-side reference for the most common hardware description language constructs. Search to filter by construct name.

Module / entity declaration

Verilog

module and_gate(input a, b, output y);

VHDL

entity and_gate is
  port(a,b: in std_logic; y: out std_logic);
end entity;

Implementation body

Verilog

// same module body

VHDL

architecture rtl of and_gate is
begin
  ...
end architecture rtl;

Concurrent clocked block

Verilog

always @(posedge clk)

VHDL

process(clk)
begin
  if rising_edge(clk) then

Signal assignment (sequential)

Verilog

q <= d;  // non-blocking

VHDL

q <= d;  -- signal assignment

Variable assignment (combinational scratch)

Verilog

tmp = a & b;  // blocking

VHDL

tmp := a and b;  -- variable assignment

If statement

Verilog

if (rst) q <= 0;
else q <= d;

VHDL

if rst = '1' then
  q <= '0';
else
  q <= d;
end if;

Case statement

Verilog

case (sel)
  2'b00: y = a;
  2'b01: y = b;
endcase

VHDL

case sel is
  when "00" => y <= a;
  when "01" => y <= b;
end case;

Single-line comment

Verilog

// this is a comment

VHDL

-- this is a comment

Constant declaration

Verilog

parameter WIDTH = 8;

VHDL

constant WIDTH : integer := 8;

Multi-bit vector/bus

Verilog

wire [7:0] data;

VHDL

signal data : std_logic_vector(7 downto 0);

Sub-module instantiation

Verilog

and_gate u1 (.a(x), .b(y), .y(z));

VHDL

u1: and_gate port map (a=>x, b=>y, y=>z);

AND / OR / NOT operators

Verilog

y = a & b;
y = a | b;
y = ~a;

VHDL

y <= a and b;
y <= a or b;
y <= not a;

About the Verilog vs VHDL Syntax Reference

Verilog and VHDL describe the same underlying hardware concepts with different syntax. This reference lines up the most common constructs side by side so you can translate between the two languages quickly.

The assignment operator trap

Verilog's blocking (=) vs non-blocking (<=) and VHDL's variable (:=) vs signal (<=) assignments look similar but behave differently inside clocked logic. Using the wrong form in sequential (clocked) logic is the single most common cause of a design that simulates correctly but synthesizes into different, broken hardware — always use non-blocking/signal assignment for clocked flip-flop logic in both languages.

Frequently asked questions

Can I mix Verilog and VHDL in the same project?

Yes — most synthesis and simulation tools support mixed-language projects, instantiating a VHDL entity from a Verilog module or vice versa. This is common when integrating a third-party IP block written in one language into a project primarily written in the other.

Why does VHDL need explicit type conversions that Verilog does not?

VHDL's strong typing requires explicit conversion functions (like std_logic_vector to unsigned) when connecting signals of different types, catching a class of connection errors at compile time. Verilog's looser typing lets you connect signals more freely, which is faster to write but catches fewer mistakes automatically.

Related tools & guides

Verilog vs VHDL Comparison Guide →Logic Gate & Truth Table Builder →