The full RTL-to-GDSII flow, static timing analysis and timing closure, physical verification signoff, tape-out and mask generation, and the real economics of committing to custom silicon versus staying on an FPGA.
Turning verified RTL into fabricated silicon means passing through synthesis, floorplanning, placement, clock tree synthesis, and routing, with static timing analysis checking every path against the clock at each step. This module walks the entire RTL-to-GDSII flow stage by stage, explains why a setup violation and a hold violation demand very different fixes, and covers the design-rule, connectivity, and power-integrity checks a layout has to pass before it can be signed off for tape-out.
By the end of this module you should be able to explain why a single RTL bug found after tape-out can mean a full re-spin, and why the ASIC-versus-FPGA decision ultimately comes down to production volume against non-recurring engineering cost. This module builds directly on Module 4's FPGA-vs-ASIC framing, and Module 13's semiconductor manufacturing content covers the physical fabrication this flow's later stages hand off to.