Semiconductor & Digital Electronics System Architecture
The full 8-step end-to-end digital & semiconductor design lifecycle (architect & specify, design & model, simulate & verify, synthesize & optimize, implement P&R, signoff & tapeout, fabricate & package, and deploy & operate), the six core disciplines that make up the practice (digital logic design, hardware description languages, FPGA design & prototyping, ASIC design flow from RTL to GDSII, semiconductor manufacturing, and packaging & test), a typical digital system architecture, the FPGA/ASIC implementation paths, a design verification stack, and the EDA & tool ecosystem that ties chip design, verification, and fabrication together in production. Hover, tap, or focus any component for its description and standard reference.
Hover, tap, or focus any component on the drawing (or a circuit below it) for details. Click to pin; move away or click again to clear.
Component Reference
Every component in the diagram above, grouped by section, with its role and the relevant standard.
Inputs
Product Requirements & Specifications
The starting brief for the chip or board: target market, functions, performance envelope, and constraints that everything downstream must satisfy.
System Architecture & Interfaces
The high-level partition of the system into blocks and the interfaces (buses, protocols, pinout) between them, set before RTL work begins.
Performance Targets (Speed, Power, Area)
The PPA (Power, Performance, Area) budget the design must hit — target clock frequency, power envelope, and silicon/die area or FPGA resource ceiling.
Technology Node (Process / PDK)
The chosen silicon process node and its Process Design Kit (PDK) — defines transistor models, design rules, and what's physically achievable.
I/O Standards & Protocols
The external interface standards the design must speak — e.g. PCIe, USB, Ethernet, DDR — which drive I/O cell selection and timing budgets.
Test, DFT & Reliability Requirements
Design-for-test and reliability requirements set up front — scan coverage targets, ATPG strategy, and reliability/qualification standards to meet.
Cost, Volume & Schedule Targets
The business constraints — unit cost target, production volume, and time-to-market schedule — that shape the FPGA-vs-ASIC decision and process choice.
Outcomes
High Performance & Efficiency
A design that hits its clock-speed and throughput targets while making efficient use of silicon area and switching power.
Low Power Consumption
A chip or board that meets its power budget — critical for battery-powered, thermally constrained, or high-density data-center applications.
Reliable Products at Scale
Consistent, defect-free operation across the full production volume and product lifetime, validated by DFT, burn-in, and field reliability data.
Lower Unit Cost (High Volume ASIC)
Moving a proven design from FPGA to ASIC amortizes NRE across volume, driving down the per-unit cost for high-volume production.
Faster Time to Market
FPGA prototyping, IP reuse, and mature EDA flows compress the path from architecture to working silicon or shipping board.
Competitive Advantage
Custom silicon and optimized digital design differentiate a product on performance, power, size, or cost in ways commodity parts can't match.
Digital & Semiconductor Design Lifecycle
1. Architect & Specify
Define functionality & features, microarchitecture & partitions, performance & power budgets, clocking/resets/interfaces, and technology & IP selection — the blueprint the rest of the flow builds from.
📘 IEEE 1800 (SystemVerilog)2. Design & Model
RTL design in Verilog/VHDL/SystemVerilog: FSMs, datapaths, and algorithms coded and integrated with reused IP, backed by a testbench and verification plan and design reviews.
📘 IEEE 1364 / IEEE 10763. Simulate & Verify
Functional simulation, assertions & coverage, formal verification (SVA/PSL), UVM/constrained-random testing, and lint/CDC/RDC checks confirm the RTL behaves correctly before synthesis.
📘 IEEE 1800.2 (UVM)4. Synthesize & Optimize
RTL synthesis turns behavioral code into gates, guided by timing constraints (SDC); area, power, and timing reports plus gate-level simulation and ECO optimization refine the netlist.
5. Implement (P&R)
Floorplanning & power grid, placement, clock-tree synthesis (CTS), routing, and timing closure turn the gate-level netlist into a physical layout.
6. Signoff & Tapeout
STA timing signoff, DRC/LVS/ERC, IR-drop/EM/SI-PI signoff, and DFT/ATPG signoff clear the design for GDSII tapeout — the point of no return before fabrication.
7. Fabricate & Package
Wafer fabrication in the fab, wafer sort & test, dicing & packaging, burn-in & final test, and readiness for board assembly turn the layout into physical parts.
📘 JEDEC (Packaging & Reliability)8. Deploy & Operate
Board bring-up & validation, field performance monitoring, firmware updates (for FPGA/SoC designs), and yield & reliability feedback close the loop into the next design iteration.
Feedback Loop
Requirements, test results, silicon data, and field feedback all loop back to the front of the lifecycle — each tapeout and each field deployment informs the next design's specs, verification plan, and IP choices.
Digital Logic Design
Combinational Logic
The fundamental building blocks — AND, OR, XOR, and MUX gates — whose output depends only on current inputs. Boolean algebra and logic minimization reduce these to the smallest, fastest gate count.
Sequential Logic
D flip-flops, registers, and finite state machines whose output depends on stored state as well as current inputs — the basis of counters, FIFOs, and control logic.
Digital Logic Fundamentals
Boolean algebra & logic minimization, FSMs/counters/registers/FIFOs, timing fundamentals (setup, hold, metastability), and clock domain crossing (CDC) — the theory every digital designer needs before writing RTL.
Key Output: Correct, Efficient Digital Logic
The deliverable of this discipline: correctness-verified, area/power-efficient combinational and sequential logic ready to be captured in HDL.
Hardware Description Languages
Verilog
An IEEE 1364 hardware description language used to model digital circuits at the register-transfer level — modules, always blocks, and continuous assignments describe synthesizable logic like the adder shown.
📘 IEEE 1364VHDL
An IEEE 1076 hardware description language with strong typing and an Ada-derived syntax — entities, architectures, and signal assignments (e.g. sum <= unsigned(a) + unsigned(b)) describe the same synthesizable logic as Verilog.
📘 IEEE 1076HDL Design Practices
RTL coding for synthesizability, testbenches with assertions and coverage, SystemVerilog/VHDL-2008 features, and IP reuse & parameterization — the practices that make HDL code both correct and maintainable.
Key Output: Synthesizable RTL Code
The deliverable of this discipline: clean, synthesizable RTL in Verilog, VHDL, or SystemVerilog ready to be prototyped on FPGA or pushed through the ASIC synthesis flow.
FPGA Design & Prototyping
Xilinx Vivado
AMD/Xilinx's FPGA design suite — synthesis, implementation (place & route), and debug (ILA/SignalTap-class tools) for Xilinx FPGA and SoC families.
Intel Quartus Prime
Intel's FPGA design suite for its FPGA and SoC device families — synthesis, place & route, and debug tooling equivalent in role to Xilinx Vivado.
FPGA Prototyping Board
A physical FPGA development board used for quick bring-up and hardware validation of a design before (or instead of) committing to an ASIC.
FPGA Design Practices
Quick bring-up & prototyping, soft processors (MicroBlaze, Nios II), IP cores (DSP, DDR, PCIe, Ethernet), debug with ILA/SignalTap, and iterative hardware validation on real silicon.
Key Output: Working Prototype on FPGA
The deliverable of this discipline: a working, hardware-validated prototype on FPGA — proof the RTL functions correctly before an ASIC commitment.
ASIC Design Flow (RTL → GDSII)
RTL (Verilog/VHDL/SV)
The synthesizable register-transfer-level description that is the starting point of the ASIC implementation flow — the same RTL that was simulated and prototyped on FPGA.
Synthesis (Logic Optimization)
Logic synthesis maps RTL to a technology-specific gate-level netlist, optimizing for the target timing, area, and power constraints (SDC).
Place & Route (Physical Implementation)
Physical implementation places standard cells on the die and routes the interconnect between them, closing timing while meeting power and congestion constraints.
GDSII (Manufacturing Layout)
The final manufacturing layout format handed to the foundry — GDSII fully specifies every mask layer needed to fabricate the chip.
Signoff & Verification Checks
The signoff gauntlet run alongside implementation: timing analysis (STA), power analysis (IR-drop/EM), DRC/LVS/ERC, physical verification, DFT (scan, ATPG, BIST), and formal & equivalence checking — every check that must pass before tapeout.
Key Output: GDSII Ready for Fabrication
The deliverable of this discipline: a fully signed-off GDSII layout ready to be handed to a wafer fab for fabrication.
Semiconductor Manufacturing
Photolithography (Exposure)
Light exposed through a patterned mask transfers the circuit geometry onto a photoresist-coated wafer — the step that defines every feature on the chip.
Doping (Ion Implant)
Ion implantation embeds dopant atoms into exposed silicon regions to form the n-type and p-type regions that make transistors work.
Etching (Remove Material)
Chemical or plasma etching removes material selectively, cutting the patterned photoresist openings down into the underlying layer.
Deposition (Add Layers)
Thin films of conductor, insulator, or semiconductor material are deposited across the wafer, building up the layers that form transistors and interconnect.
CMP (Planarization)
Chemical-mechanical planarization polishes the wafer surface flat between layers, essential for the many interconnect layers stacked on modern chips.
Repeat (10s–100s of Layers)
The photolithography → doping/deposition → etch → CMP cycle repeats tens to hundreds of times to build up all the transistor and interconnect layers of a modern chip.
Fab Process & Test
Transistor formation (MOSFET), interconnect layers (metallization), wafer test (probe), and yield/defects & process control — the steps and metrics that turn a patterned wafer into known-good die.
Key Output: Tested Silicon Wafer (Good Dies)
The deliverable of this discipline: a fabricated, wafer-sort-tested wafer with known-good die ready for dicing and packaging.
Packaging & Test
Die
The individual, diced piece of silicon cut from the wafer — a bare, unpackaged chip containing the fabricated circuit.
Package
The die is attached, wire-bonded or bumped, and encapsulated in a protective package (e.g. QFP, BGA, QFN) that provides mechanical protection and external pin connections.
Final Chip
The fully packaged, tested, and marked chip — ready for board assembly and shipment to customers.
Assembly & Test Steps
Die attach & wire bond/bump, encapsulation/molding, final test (ATE), burn-in & reliability screening, and board assembly (SMT/BGA) — the steps that turn a good die into a reliable, board-ready component.
Key Output: Reliable Chips for Systems
The deliverable of this discipline: a fully packaged, tested, and reliability-screened chip ready to be assembled onto a board and deployed in a system.
Typical Digital System Architecture
Sensors / Inputs
The physical-world signal sources — sensors and other analog or digital inputs — that feed the system's front end.
ADC
The Analog-to-Digital Converter that samples and quantizes an analog input into a digital word the digital logic can process.
Digital Logic (Processing)
The core digital processing block — combinational and sequential logic (custom RTL, a soft/hard processor, or both) that implements the system's function.
Memory (SRAM / DRAM)
On-chip SRAM and/or external DRAM that store working data and, in processor-based designs, instructions — bidirectionally coupled to the digital logic.
Outputs / Actuators
Digital or driven-analog outputs — GPIO, actuator drivers, displays, or communication interfaces — through which the system acts on the physical world.
Clock Generator
Generates and distributes the system clock(s) — often a PLL/oscillator-based block — that synchronizes every sequential element in the design.
Reset Manager
Sequences and synchronizes reset across the design, ensuring every block starts from a known, glitch-free state.
Power Management
Regulates and sequences supply rails, and in low-power designs may gate clocks or power domains to hit the power budget.
FPGA/ASIC Implementation Paths
RTL (FPGA Path)
The same synthesizable RTL as the ASIC path, entering the FPGA vendor toolchain (Vivado/Quartus) instead of the ASIC synthesis/P&R flow.
Synthesis (FPGA)
FPGA logic synthesis maps RTL onto the target device's LUTs, flip-flops, and dedicated blocks (DSP, block RAM).
Implementation (Mapping, P&R)
Technology mapping and place & route assign the synthesized logic to specific physical LUTs/FFs on the device and route the interconnect between them.
Bitstream
The final configuration file that programs the FPGA's LUTs, routing, and I/O — generated after implementation and loaded at power-up.
FPGA Device
The programmable device itself, configured by the bitstream to implement the design — reprogrammable, in contrast to a fixed ASIC.
RTL (ASIC Path)
The same RTL entering the ASIC flow instead of the FPGA toolchain — a fixed, non-reprogrammable implementation target.
ASIC Flow (Synth → P&R)
The full ASIC synthesis-through-place-and-route flow (see the ASIC Design Flow discipline panel above) compressed into one step of this path diagram.
GDSII (ASIC Path)
The manufacturing layout produced by the ASIC flow, handed off to the foundry for fabrication.
Fabrication
The wafer fabrication process (see the Semiconductor Manufacturing discipline panel) that turns the GDSII layout into physical silicon.
ASIC Device
The fixed-function fabricated chip — cannot be reprogrammed, but offers better PPA and lower per-unit cost at volume than an equivalent FPGA.
Design Verification Stack
Requirements & Spec
The verification plan starts from the same requirements and architecture spec that drove RTL design — the reference against which correctness is judged.
Test Plan
A structured plan enumerating every feature, corner case, and coverage goal the verification environment must exercise before signoff.
Testbench (UVM)
A Universal Verification Methodology (UVM) class-based, constrained-random testbench that drives and checks the design under test.
📘 ISO/IEC 1800 (UVM)Simulation (Functional)
Event-driven functional simulation executes the testbench against the RTL, exercising directed and constrained-random test scenarios.
Coverage & Metrics
Functional and code coverage metrics quantify how much of the design and spec have actually been exercised — the data-driven measure of verification completeness.
Assertions (SVA/PSL)
SystemVerilog Assertions (SVA) or PSL embedded in the RTL or testbench continuously check protocol and design invariants during simulation.
Formal Verification
Formal methods mathematically prove properties hold for all possible input sequences, exhaustively — complementing simulation's sampled coverage.
Lint & CDC Checks
Static lint catches coding and style issues early; clock-domain-crossing (CDC) analysis finds unsynchronized signals crossing between clock domains before they cause silicon bugs.
Equivalence Checking
Formal equivalence checking proves the gate-level netlist (post-synthesis or post-ECO) is logically identical to the RTL it was derived from.
EDA & Tool Ecosystem
Synopsys Design Compiler
A leading RTL logic synthesis tool from Synopsys, mapping RTL to a technology-specific gate-level netlist.
Cadence Genus
Cadence's RTL synthesis solution, an alternative to Design Compiler in the Design & RTL stage.
Siemens Precision
Siemens EDA's RTL synthesis tool (Precision), part of the Design & RTL toolchain.
Synopsys VCS
A widely used Verilog/SystemVerilog event-driven simulator from Synopsys for functional verification.
Cadence Xcelium
Cadence's high-performance simulation engine for RTL and gate-level verification.
Siemens Questa
Siemens EDA's simulation and verification platform (Questa), supporting UVM-based testbenches.
Synopsys IC Compiler II
Synopsys's place-and-route and physical implementation tool for advanced-node ASIC design.
Cadence Innovus
Cadence's digital implementation system for place & route, optimization, and physical signoff.
Siemens Aprisa
Siemens EDA's place-and-route tool (Aprisa) for physical implementation.
PrimeTime (STA)
Synopsys PrimeTime — the industry-standard static timing analysis (STA) signoff tool.
Calibre (DRC/LVS)
Siemens EDA's Calibre — the industry-standard physical verification (DRC/LVS) signoff tool.
JasperGold (Formal)
Cadence JasperGold — a leading formal property verification and equivalence-checking signoff tool.
DFT Compiler (ATPG)
Synopsys DFT Compiler — scan insertion and Automatic Test Pattern Generation (ATPG) for manufacturing test.
Popular Software & Platforms
AutoCAD (2D CAD)
Autodesk AutoCAD — general-purpose 2D drafting, used for board outlines, mechanical drawings, and system diagrams around the electronics.
SOLIDWORKS (3D CAD)
Dassault Systèmes SOLIDWORKS — parametric 3D CAD used for enclosure and mechanical design around a board or module.
Autodesk Inventor (3D CAD)
Autodesk Inventor — parametric 3D mechanical CAD, an alternative to SOLIDWORKS for enclosure and fixture design.
Creo (3D CAD)
PTC Creo — parametric 3D CAD software used for mechanical design and enclosure modeling.
CATIA (3D CAD)
Dassault Systèmes CATIA — high-end 3D CAD used in aerospace and automotive electronics packaging and enclosure design.
Autodesk Fusion 360 (3D CAD)
Autodesk Fusion 360 — cloud-based 3D CAD/CAM combining mechanical design with manufacturing workflows.
Ansys (Simulation FEA/CFD)
Ansys — multiphysics simulation suite (thermal, structural, EM) used to validate a board or enclosure design before it's built.
COMSOL (Simulation)
COMSOL Multiphysics — coupled-physics simulation, including electromagnetic and thermal analysis relevant to chip/board design.
Simulia Abaqus (Simulation)
Dassault Systèmes Simulia Abaqus — finite-element structural and thermal simulation, used for mechanical/thermal validation.
MathWorks MATLAB (Numerical/Modeling)
MathWorks MATLAB — numerical computing and algorithm development, widely used for DSP, control, and signal-processing modeling before RTL capture.
Simulink (Numerical/Modeling)
MathWorks Simulink — block-diagram modeling and simulation, often used for system-level and HDL Coder-driven design.
Xilinx Vivado (FPGA)
AMD/Xilinx Vivado — the FPGA design suite also shown in the FPGA Design & Prototyping discipline panel above.
Intel Quartus Prime (FPGA)
Intel Quartus Prime — the FPGA design suite also shown in the FPGA Design & Prototyping discipline panel above.
Altium Designer (PCB/EDA)
Altium Designer — a leading PCB design and schematic capture tool for laying out the board that a chip lands on.
KiCad (PCB/EDA)
KiCad — a free, open-source schematic capture and PCB layout suite widely used from hobbyist to professional PCB design.
PSpice / LTspice (Circuit Simulation)
SPICE-family circuit simulators (PSpice, LTspice) used to simulate analog and mixed-signal circuit behavior before board fabrication.
Essential Skills
Digital logic & FSM design
Fluency in combinational and sequential logic design and finite state machines — the foundation every downstream digital-design skill builds on.
Verilog / VHDL / SystemVerilog
Working proficiency in at least one HDL to capture, simulate, and synthesize digital designs.
Timing analysis & constraints
The ability to write correct SDC constraints and interpret static timing analysis reports to close timing.
FPGA design & debugging
Skill with FPGA toolchains (Vivado/Quartus) and in-system debug (ILA/SignalTap) for hardware bring-up.
ASIC design flow understanding
Familiarity with the RTL-to-GDSII flow — synthesis, P&R, and signoff — even for engineers who specialize in one stage.
Scripting (Tcl, Python, Perl)
Scripting fluency to automate EDA tool flows, process reports, and build regression infrastructure.
Electronics fundamentals
Grounding in analog and digital circuit theory that underlies both chip and board-level design.
Semiconductor device basics
Understanding of diode, BJT, and MOSFET device physics that determines how the transistors underneath the logic actually behave.
Signal integrity & power integrity
Awareness of how high-speed signals and power delivery networks behave on real silicon and boards, not just in idealized simulation.
DFT & test methodologies
Knowledge of scan insertion, ATPG, and BIST techniques that make a design testable in high-volume manufacturing.
Skills & KPIs
Max Clock Frequency (MHz)
The highest clock frequency the design achieves after timing closure — a headline speed metric.
Power Consumption (mW)
Total switching and static power draw — measured against the power budget set in the Inputs.
Area (mm² / Gates)
Die area or gate count consumed by the design — determines ASIC cost and FPGA resource fit.
Timing Slack (ns)
The margin (positive or negative) between required and actual arrival time on the critical path.
Yield / Defect Rate (%)
The fraction of manufactured die that pass test — a key measure of process maturity and design robustness.
FPGA Resource Utilization (%)
The fraction of LUTs, flip-flops, BRAM, and DSP slices consumed on the target FPGA device.
Simulation Coverage (%)
Functional and code coverage achieved in simulation — a proxy for verification completeness.
Test Coverage (%)
The fraction of manufacturing defects the DFT scan/ATPG patterns are able to detect.
Time to Tapeout
Elapsed schedule time from RTL freeze to GDSII tapeout — a project-velocity metric.
First-Pass Silicon Success
Whether the fabricated silicon meets spec on the first spin, without requiring a costly re-spin.
Standards & Reference
IEEE 1364 — Verilog HDL
The IEEE standard defining the Verilog hardware description language.
📘 IEEE 1364IEEE 1076 — VHDL
The IEEE standard defining the VHDL hardware description language.
📘 IEEE 1076IEEE 1800 — SystemVerilog
The IEEE standard defining SystemVerilog, unifying design and verification constructs (including assertions).
📘 IEEE 1800ISO/IEC 1800 (UVM)
The standardized Universal Verification Methodology base class library for testbench construction.
📘 IEEE 1800.2 / Accellera UVMASME Y14.5 — GD&T
The geometric dimensioning & tolerancing standard used for mechanical drawings of enclosures and packages.
📘 ASME Y14.5ISO 10303 (STEP) — CAD Exchange
The STEP standard for exchanging 3D CAD model data between different mechanical CAD systems.
📘 ISO 10303JEDEC — Packaging & Reliability
JEDEC standards governing IC package outlines, moisture sensitivity, and reliability qualification.
📘 JEDECIPC-2221 / 2581 — PCB Standards
IPC standards for generic PCB design (2221) and design data exchange (2581).
📘 IPC-2221 / IPC-2581Career Paths & Application Areas
Consumer Electronics
Smartphones, wearables, and home electronics — high-volume, cost- and power-sensitive digital/ASIC design.
Automotive
Engine control, ADAS, and infotainment electronics — subject to automotive-grade reliability and functional-safety requirements.
Aerospace & Defense
Radiation-tolerant and mission-critical digital electronics for avionics, satellites, and defense systems.
Industrial Automation
PLC, motor-control, and sensor-interface electronics for factory and process automation.
Communications
Baseband, RF-adjacent, and networking silicon for wired and wireless communication infrastructure.
Medical Devices
Digital electronics for diagnostic and therapeutic devices, subject to medical-grade reliability standards.
AI / Data Centers
High-performance ASICs and FPGAs for AI acceleration, networking, and data-center compute.
IoT & Edge Devices
Low-power, cost-optimized digital designs for connected sensors and edge-compute devices.
Digital Design Engineer
Designs RTL and digital logic — the core role spanning the Digital Logic Design and HDL disciplines.
FPGA Design Engineer
Specializes in FPGA-targeted RTL design, timing closure, and in-system debug.
ASIC Design Engineer
Focuses on the ASIC RTL-to-GDSII flow — synthesis, place & route, and physical implementation.
Verification Engineer
Builds UVM testbenches and formal environments to prove RTL correctness before tapeout.
Physical Design Engineer
Owns floorplanning, place & route, and timing/power closure in the physical implementation flow.
DFT Engineer
Designs scan chains, ATPG patterns, and BIST logic to make chips testable in volume manufacturing.
Hardware Architect
Defines system architecture, microarchitecture, and performance/power budgets at the top of the lifecycle.
Chip Design Manager
Leads chip design teams and schedules across the full architecture-to-tapeout lifecycle.
Best Practices
Design with Correctness First
Get the logic and functionality right before optimizing for speed or area — premature optimization on incorrect logic wastes far more time than it saves.
Verify Early, Verify Often
Start writing testbenches and running simulation alongside RTL development, not after — bugs found early are exponentially cheaper to fix.
Prototype on FPGA, Then Decide ASIC
Validate the design on FPGA hardware before committing to the far more expensive and irreversible ASIC tapeout.
Close Timing with Margin
Leave positive timing margin rather than closing at exactly zero slack — process, voltage, and temperature variation will eat into it.
Automate & Script Your Flow
Script the synthesis-through-signoff flow (Tcl/Python) so it's repeatable, regression-testable, and not dependent on manual GUI steps.
Test for Reliability & Yield
Design DFT and burn-in screening in from the start — reliability and yield are design decisions, not just manufacturing outcomes.
Document Everything
Keep specs, design decisions, and verification plans documented and current — essential for team handoff and audit/reuse.
Iterate & Learn Continuously
Feed field data, yield data, and lessons learned back into the next design's requirements and verification plan.
Connections & Flows
The signal and data flows that tie the diagram together — each shown as a colored line in the legend above.
Feedback Loop
Requirements, test results, silicon data, and field feedback loop from later lifecycle stages back to Architect & Specify and Design & Model — each tapeout and field deployment informs the next design iteration.
📘 Continuous improvement loop