A full printed-circuit-board design studio in your browser — browse a component reference, generate boards from templates or a plain-English description, then place, route (Lee autorouter), design-rule-check, and export Gerber / KiCad / SVG. No account or API key required.
Create a board from scratch in the CAD Editor, start from a Template, generate one from a description in the Design Generator, or drop in a part from the Reference library.
This browser-based PCB design studio lets engineers place components, route traces, run design rule checks, and export Gerber files — all without installing software. Engineers use it to prototype printed circuit board layouts, check trace current capacity per IPC-2221, and generate fabrication-ready outputs for services like JLCPCB and PCBWay.
PCB trace current capacity is governed by IPC-2221 (formerly IPC-D-275), which defines the relationship between trace width, copper weight (oz/ft²), temperature rise, and maximum current. The standard formula for external traces is: I = K × ΔT^0.44 × A^0.725, where I is current in amperes, K = 0.048 for external layers (0.024 for internal), ΔT is the allowable temperature rise above ambient in °C, and A is the cross-sectional area in mils².
Cross-sectional area depends on trace width (mils) and copper weight: A = Width × Thickness, where 1 oz/ft² copper = 1.37 mils thick, 2 oz/ft² = 2.74 mils. A 20-mil wide trace on 1 oz external copper with a 10°C temperature rise carries approximately 1.5 A. Doubling the copper weight roughly doubles the current capacity for the same trace width.
Design rules (clearances, trace widths, via sizes) are governed by IPC-2221 for standard boards and by individual fabricator specifications (e.g., JLCPCB requires minimum 0.127 mm trace width and 0.127 mm clearance).
IPC-2221 (Generic Standard on Printed Board Design) is the primary design standard governing trace widths, spacing, via sizes, and material specifications. IPC-7351 defines land pattern and footprint requirements for surface-mount components. IPC-A-600 covers the acceptability of printed boards. UL 796 governs printed circuit board materials for use in electronic equipment. For aerospace applications, MIL-PRF-31032 and IPC-6012 Class 3 impose tighter design rules. RoHS Directive 2011/65/EU restricts hazardous substances (lead, cadmium, mercury) in PCB finishes.
Power traces carrying high current must be wide enough to limit resistive losses and temperature rise. A rule of thumb: 1 oz copper, external trace, 10°C rise — approximately 30 mils (0.75 mm) per amp. Internal traces require twice the width for the same current.
Ground planes dramatically reduce EMI, provide low-impedance return paths, and improve thermal performance. Differential pair routing requires matched trace lengths within 5 mils for high-speed signals. Via current capacity must also be checked — a 0.3 mm drill via on 1 oz copper carries approximately 0.5 A. For multi-layer boards, thermal vias in a 3×3 grid pattern under power ICs reduce junction-to-board thermal resistance by 30–50%.
Select a starting approach: browse the component Reference library and drop a part onto a board, generate a board from a template by choosing a circuit type and parameters, or describe your board in plain English in the Design Generator. Once a board is open in the CAD Editor, use Place mode to add components from the palette, Route mode to draw traces between pads, and Auto-route to have the Lee wave-propagation router connect all nets automatically. Run DRC to check clearance, trace width, short circuits, and unrouted nets. Export Gerber RS-274X files for fabrication.
2 oz/ft² copper is recommended for power traces carrying more than 2–3 A. For high-current applications (>10 A), use 3–4 oz copper or use multiple parallel traces. Signal traces on the same board can remain on 1 oz copper layers, with power on dedicated 2 oz layers.
Per IPC-2221, the minimum external conductor spacing for 48V (unpopulated board) is 0.4 mm (15.7 mils) for B1 category. For a coated board operating at altitude below 3050 m, 0.25 mm (10 mils) is acceptable. Mains voltage (120/240V) requires ≥1.5 mm clearance to meet IPC-2221 and safety standards.
Use the Export button and select Gerber RS-274X. The export generates separate files for F.Cu (front copper), B.Cu (back copper), F.Mask, B.Mask, F.Silkscreen, Edge.Cuts (board outline), and Excellon drill file — the complete set required by JLCPCB, PCBWay, and most other fabricators. Select the JLCPCB rules preset in Settings for compatible minimum trace/clearance values.
A ratsnest shows unrouted connections between component pads that share the same net. Each dashed line represents a connection that must be routed with a trace. Use Auto-route to connect all nets automatically, or use Route mode to draw traces manually. DRC will flag any remaining unconnected nets after routing.
Vias transition traces between copper layers. Use them when a trace cannot complete its path on one layer without crossing another trace. The Lee autorouter adds vias automatically when needed. Thermal vias (typically 0.3 mm drill, 0.6 mm pad) placed in a grid under power ICs conduct heat from the component to inner copper planes, improving thermal management.
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