Why These Terms Matter

Semiconductor and electronics engineering runs on a dense vocabulary that spans physics, materials science, digital logic, and manufacturing — and a single term can mean the difference between a working design and a costly re-spin. A datasheet that specifies "propagation delay" versus "settling time," or a process node described in terms of "gate pitch" rather than a marketing name, carries precise engineering meaning that affects timing closure, power budgets, and yield. Engineers moving between analog design, digital logic, RF, and fabrication need a shared, accurate vocabulary to read datasheets, review schematics, communicate with foundries, and pass certification exams.

This glossary defines 55 of the most frequently used semiconductor and electronics terms and acronyms, organized alphabetically, with the standards bodies (IEEE, JEDEC, SEMI) or industry conventions that formalize them where applicable. It is written for practicing electrical and electronics engineers, embedded systems developers, and students preparing for the FE/PE electrical exams or industry certifications.

A

ASIC (Application-Specific Integrated Circuit) — semiconductor industry term
An integrated circuit custom-designed for a single, specific application rather than for general-purpose use, as opposed to an FPGA which is reconfigurable. ASICs offer the lowest per-unit cost, highest performance, and lowest power at high volume, but require a costly and irreversible mask set and fabrication run (a "tape-out"). ASIC design flows move from RTL (register-transfer level) code through synthesis, place-and-route, and verification before committing to silicon.
Ampacity (of a PCB trace) — IPC-2221
The maximum current a printed circuit board trace can carry continuously without exceeding an allowable temperature rise, typically 10°C or 20°C above ambient. Ampacity depends on trace width, copper thickness (in ounces per square foot), whether the trace is on an internal or external layer, and airflow. IPC-2221 provides the standard charts and formulas used to size traces for a given current.
Analog-to-Digital Converter (ADC) — general electronics term
A circuit that converts a continuous analog voltage or current into a discrete digital code. Key ADC specifications include resolution (bits), sampling rate, and effective number of bits (ENOB), which accounts for real-world noise and distortion that reduce the converter's usable precision below its nominal bit count.
Bandgap (Energy Bandgap, Eg) — semiconductor device physics
The energy difference between the valence band and the conduction band of a material, measured in electron-volts (eV), which determines whether a material behaves as a conductor, semiconductor, or insulator. Silicon has a bandgap of about 1.12 eV; gallium nitride (GaN) is about 3.4 eV, and silicon carbide (SiC) is about 3.3 eV — the much wider bandgap of GaN and SiC is why they support higher breakdown voltages and higher switching frequencies in power electronics.

B

Bandgap Reference — analog IC design term
A voltage reference circuit that produces a stable output voltage (commonly ~1.2 V) largely independent of temperature and supply voltage, by summing a voltage that increases with temperature (proportional to absolute temperature, PTAT) with one that decreases with temperature (complementary to absolute temperature, CTAT). Bandgap references are the standard building block for regulators, ADCs, and DACs that need a stable internal reference.
BGA (Ball Grid Array) — IC packaging term
A surface-mount IC package that uses an array of solder balls on the underside of the package instead of leads around the perimeter, allowing far higher pin density than QFP-style packages. BGAs require X-ray or cross-section inspection to verify solder joint quality since the connections are hidden beneath the package body.
BJT (Bipolar Junction Transistor) — semiconductor device term
A three-terminal (base, collector, emitter) transistor that uses both electron and hole charge carriers, controlled by a base current rather than a gate voltage as in a MOSFET. BJTs typically offer higher transconductance and better matching for analog applications but draw continuous base current, unlike the voltage-controlled, near-zero static gate current of a MOSFET.
Bond Wire — IC packaging term
A fine wire, typically gold, copper, or aluminum, that electrically connects a die's bond pads to the package leadframe. Bond wire inductance (typically 1-2 nH per millimeter) becomes a significant parasitic element at high switching frequencies, motivating flip-chip and wire-bond-free packaging for high-speed and high-power devices.

C

CMOS (Complementary Metal-Oxide-Semiconductor) — IC fabrication technology
A fabrication technology that pairs PMOS and NMOS transistors to build logic gates that draw significant current only while switching, giving CMOS its dominant advantage of very low static power consumption. Nearly all modern digital ICs — microprocessors, memory, FPGAs — are fabricated in CMOS.
Crosstalk — signal integrity term
Unwanted coupling of a signal from one conductor (the aggressor) onto an adjacent conductor (the victim) through mutual capacitance and inductance. Crosstalk grows with trace-to-trace proximity, parallel run length, and signal edge rate, and is controlled in PCB layout through spacing rules (commonly the "3W rule": trace spacing at least three times the trace width) and ground-plane shielding.
Current Mirror — analog IC design term
A circuit configuration that reproduces a reference current in one branch as a copy (mirrored) current in another branch, typically using matched transistors. Current mirrors are a fundamental analog building block used for biasing amplifier stages and setting bias currents without dedicated resistors at every node.
Cutoff Frequency (fT) — transistor/RF term
The frequency at which a transistor's current gain drops to unity (1, or 0 dB), used as a figure of merit for how fast a device can amplify or switch. A higher fT indicates a faster process node or device suitable for RF and high-speed digital applications.

D

DAC (Digital-to-Analog Converter) — general electronics term
A circuit that converts a digital code into a corresponding analog voltage or current. Key specifications include resolution, settling time (how quickly the output stabilizes after a code change), and glitch energy (unwanted transient spikes during code transitions).
Depletion Region — semiconductor device physics
The region at a p-n junction where mobile charge carriers have been depleted, leaving fixed ionized dopant atoms that create an internal electric field. The width of the depletion region increases with reverse bias voltage and determines a diode's or MOSFET's junction capacitance and breakdown voltage.
Differential Pair — signal integrity / PCB layout term
Two traces carrying complementary signals (one the inverse of the other) that are routed with tightly controlled spacing and matched length so a receiver senses only the voltage difference between them. Differential signaling (used in USB, HDMI, PCIe, LVDS) rejects common-mode noise picked up equally by both traces, making it far more robust than single-ended signaling at high data rates.
Dopant / Doping — semiconductor manufacturing term
The intentional introduction of impurity atoms into a semiconductor crystal lattice to increase either free electrons (n-type doping, using elements like phosphorus or arsenic) or holes (p-type doping, using elements like boron). Doping concentration and profile control a device's threshold voltage, resistivity, and breakdown characteristics.
Duty Cycle — power electronics / PWM term
The fraction of a switching period during which a signal or switch is in the "on" state, expressed as a percentage. In switch-mode power supplies, duty cycle directly sets the output voltage relative to the input voltage in buck, boost, and buck-boost converter topologies.

E

ESD (Electrostatic Discharge) — reliability term, JEDEC/ANSI-ESD standards
A sudden transfer of static electric charge between objects at different potentials, capable of damaging or destroying sensitive semiconductor junctions. ICs are rated for ESD robustness using standardized test models — the Human Body Model (HBM), Charged Device Model (CDM), and Machine Model (MM) — per JEDEC JS-001 and related standards, and are protected on-chip by dedicated ESD clamp structures at every pin.
Efficiency (power conversion) — power electronics term
The ratio of output power delivered to a load versus input power drawn from the source, expressed as a percentage, with the difference dissipated as heat in switches, inductors, and parasitic resistances. Modern switch-mode converters commonly achieve 85-98% efficiency depending on topology, switching frequency, and load current.
Embedded System — general electronics term
A combination of a microcontroller or microprocessor, memory, and peripherals dedicated to running fixed or semi-fixed firmware to perform a specific function within a larger device, as opposed to a general-purpose computer. Embedded systems typically operate under real-time, power, memory, and cost constraints that shape both hardware and firmware architecture.
ENOB (Effective Number of Bits) — data converter term
A measure of an ADC's or DAC's real-world performance that accounts for noise, distortion, and nonlinearity, expressed as the number of ideal bits that would produce equivalent signal-to-noise-and-distortion ratio (SINAD). A 12-bit ADC with significant noise might have an ENOB of only 10.5 bits in practice.

F

FET (Field-Effect Transistor) — semiconductor device term
A transistor family (including MOSFETs and JFETs) in which current flow between the source and drain terminals is controlled by an electric field created by a voltage applied to the gate terminal, drawing essentially zero static gate current. FETs are the dominant switching and amplifying device in modern electronics because of their high input impedance and favorable scaling.
Flip-Chip — IC packaging term
A packaging method in which the die is mounted face-down directly onto the substrate via an array of solder bumps, eliminating bond wires entirely. Flip-chip packaging reduces parasitic inductance and enables far higher I/O density than wire-bonded packages, and is standard for high-performance processors.
FPGA (Field-Programmable Gate Array) — reconfigurable logic device
An integrated circuit containing a large array of configurable logic blocks, programmable interconnect, and I/O blocks that can be reprogrammed after manufacture to implement custom digital logic. FPGAs are configured using a hardware description language (Verilog or VHDL) synthesized into a bitstream, offering a middle ground between the flexibility of software and the speed of a fixed-function ASIC.
Fan-Out — digital logic term
The number of logic gate inputs that a single gate output can reliably drive while maintaining valid logic levels, or in advanced packaging, a chip packaging technique that redistributes I/O connections outward beyond the die footprint (fan-out wafer-level packaging, FOWLP).

G

Gate Oxide — MOSFET structure term
The thin insulating layer, historically silicon dioxide and now often a high-k dielectric, separating a MOSFET's gate electrode from the underlying silicon channel. Gate oxide thickness has scaled down to just a few atomic layers in advanced process nodes, and its integrity directly governs threshold voltage, leakage current, and long-term reliability (time-dependent dielectric breakdown, TDDB).
GaN (Gallium Nitride) — wide-bandgap semiconductor material
A wide-bandgap compound semiconductor material used to build high-electron-mobility transistors (HEMTs) that switch faster and handle higher voltages with lower losses than silicon, making GaN increasingly common in fast chargers, RF power amplifiers, and high-frequency power converters.
Ground Plane — PCB layout term
A continuous copper layer within a PCB stackup dedicated to providing a low-impedance return path for signal currents and a common reference potential. A solid, unbroken ground plane beneath high-speed traces is essential for controlled impedance and low crosstalk; slots or gaps in the plane force return currents to detour, increasing radiated emissions and signal degradation.

H

HDL (Hardware Description Language) — digital design term
A specialized programming language, principally Verilog or VHDL, used to describe the structure and behavior of digital circuits at the register-transfer level (RTL) for simulation and synthesis into gate-level netlists. HDL code is the standard entry point for both ASIC and FPGA design flows.
HEMT (High-Electron-Mobility Transistor) — compound semiconductor device
A field-effect transistor built from a heterojunction of two different semiconductor materials (commonly GaN and AlGaN) that creates a very high-mobility two-dimensional electron gas channel, enabling high-frequency, high-power operation superior to conventional silicon MOSFETs.
Hysteresis — comparator / control circuit term
A deliberate difference between the rising and falling threshold voltages of a comparator or Schmitt trigger, used to prevent output oscillation ("chatter") when the input signal is noisy near the switching threshold.

I

IGBT (Insulated-Gate Bipolar Transistor) — power semiconductor device
A power switching device that combines a MOSFET's voltage-controlled gate with a bipolar transistor's low conduction losses at high current, making it the dominant switch in medium- to high-power applications such as motor drives, inverters, and industrial power supplies above roughly 1 kW.
Impedance Matching — RF / high-speed signal term
Designing a signal path so its characteristic impedance matches the source and load impedance (commonly 50Ω for RF, 100Ω differential for high-speed digital), minimizing signal reflections at impedance discontinuities. Mismatches cause reflections that appear as ringing, overshoot, and eye-diagram closure in high-speed digital links.
Insertion Loss — RF / signal integrity term
The reduction in signal power that occurs as a signal passes through a component, connector, or transmission line, expressed in decibels (dB) as a function of frequency. Insertion loss is a key parameter in specifying cables, connectors, and PCB trace materials for high-speed and RF designs.
IP Core (Intellectual Property Core) — ASIC/FPGA design term
A reusable, pre-verified block of digital logic (such as a UART, memory controller, or CPU core) licensed or provided in HDL or netlist form for integration into a larger chip design, saving significant design and verification effort compared to building the block from scratch.

J

JEDEC — standards organization
The Joint Electron Device Engineering Council, the standards body that defines specifications for semiconductor packaging, memory interfaces (such as DDR SDRAM), and reliability test methods (including ESD and moisture sensitivity levels) used industry-wide to ensure component interoperability and qualification consistency.
Jitter — timing / signal integrity term
The deviation of a signal's timing edges from their ideal, periodic positions, measured in picoseconds or as a fraction of the bit period (unit interval). Jitter is classified as deterministic (bounded, from crosstalk or duty-cycle distortion) or random (unbounded, from thermal noise), and excessive jitter closes the timing margin in high-speed serial links.
Junction Temperature (Tj) — power device thermal term
The actual temperature at the semiconductor die junction where power is dissipated, distinct from the case or ambient temperature, calculated from power dissipation and the device's junction-to-case or junction-to-ambient thermal resistance. Keeping Tj below its rated maximum is the central constraint in power device thermal design.

L

Latch-Up — CMOS reliability term
An unintended low-impedance path between the power supply rails in a CMOS IC, created when parasitic bipolar transistors inherent in the CMOS structure turn on and form a self-sustaining short circuit, potentially destroying the device unless power is removed. Latch-up is typically triggered by voltage transients, ESD events, or overvoltage on an I/O pin, and is mitigated through guard rings and substrate contacts in the physical layout.
LDO (Low-Dropout Regulator) — power management term
A linear voltage regulator capable of maintaining regulation with a very small voltage difference between its input and output, offering low noise and simple design at the cost of dissipating the input-to-output voltage difference as heat, making it efficient only for small voltage drops.
Leadframe — IC packaging term
The metal frame within a traditional (non-BGA) IC package that provides mechanical support for the die and the external leads used to connect the package to a PCB, connected to the die via bond wires.
Lithography (Photolithography) — semiconductor fabrication term
The process of transferring a circuit pattern onto a silicon wafer using light exposure through a patterned mask onto a photosensitive resist layer, which is then developed and etched. Lithography resolution is the primary driver of process node scaling and is now performed using deep ultraviolet (DUV) and extreme ultraviolet (EUV) light sources for the smallest feature sizes.

M

MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) — semiconductor device term
A voltage-controlled transistor in which current flow between source and drain is controlled by the voltage applied to an insulated gate electrode, drawing near-zero static gate current. MOSFETs are the fundamental building block of virtually all modern digital ICs (in CMOS form) and are also widely used as power switches.
Mobility (Carrier Mobility) — semiconductor material property
A measure of how quickly electrons or holes move through a semiconductor material under an applied electric field, expressed in cm²/(V·s). Higher carrier mobility enables faster transistor switching speeds and lower on-resistance, which is why compound semiconductors like GaN and materials like strained silicon are used to boost mobility beyond bulk silicon's limits.
Moore's Law — semiconductor industry observation
The empirical observation, first stated by Gordon Moore in 1965, that the number of transistors on an integrated circuit roughly doubles every two years, historically driving corresponding gains in performance and cost-per-transistor. While transistor density scaling continues, the traditional cadence has slowed, motivating alternative scaling paths such as chiplets and advanced packaging.
MTBF (Mean Time Between Failures) — reliability engineering term
A statistical measure of the average time a repairable system or component is expected to operate between failures, typically derived from accelerated life testing and failure-rate models (such as MIL-HDBK-217 or manufacturer field data), used to predict reliability and warranty exposure.

N

NRE (Non-Recurring Engineering) Cost — semiconductor business term
The one-time design, verification, and mask-set costs incurred to develop a custom IC before any units are manufactured, as distinct from the per-unit recurring cost of fabrication. NRE cost is a central factor in the ASIC-versus-FPGA decision, since ASIC NRE (often millions of dollars for advanced nodes) is justified only at sufficiently high production volumes.
Node (Process Node) — semiconductor fabrication term
A label (such as "7 nm" or "5 nm") historically referring to the minimum feature size a fabrication process can print, though modern node names are largely marketing conventions that no longer correspond to a single physical dimension. Smaller nodes generally enable higher transistor density, lower power per switching operation, and higher clock speeds.

O

Op-Amp (Operational Amplifier) — analog circuit building block
A high-gain differential voltage amplifier with two inputs (inverting and non-inverting) and typically one output, used as the fundamental building block for analog signal conditioning circuits such as amplifiers, filters, integrators, and comparators through the addition of external feedback components.
Oscilloscope Bandwidth — test equipment term
The frequency at which an oscilloscope's measured amplitude response falls to 70.7% (-3 dB) of its true value, setting the practical upper limit on the signal frequencies and edge rates the instrument can accurately capture. A common rule of thumb requires oscilloscope bandwidth at least 3-5 times the highest frequency component of interest.

P

Package-on-Package (PoP) — advanced packaging term
A stacking technique in which one IC package (commonly memory) is mounted directly on top of another (commonly a processor) using interconnects on the top of the lower package, saving PCB area at the cost of added thermal and rework complexity.
PLL (Phase-Locked Loop) — clock generation term
A feedback control circuit that generates an output signal whose phase is locked to a reference signal, commonly used to synthesize a stable higher-frequency clock from a lower-frequency crystal reference, or to recover a clock embedded in a data stream.
PMIC (Power Management Integrated Circuit) — power electronics term
A single IC that integrates multiple power conversion and management functions — such as voltage regulators, battery charging, and power sequencing — that would otherwise require several discrete components, commonly used in battery-powered and space-constrained electronics.
Propagation Delay — digital logic timing term
The time interval between a change at a logic gate's or circuit's input and the corresponding change appearing at its output, a critical parameter in timing analysis that determines the maximum clock frequency a digital design can achieve without violating setup and hold requirements.
PWM (Pulse-Width Modulation) — power electronics / control term
A technique for encoding an analog signal level or controlling average power delivery by varying the duty cycle of a fixed-frequency switching waveform. PWM is the standard control method for switch-mode power supplies, motor drives, and LED dimming.

Q

QFN (Quad Flat No-lead) Package — IC packaging term
A leadless surface-mount package with contact pads on its underside around the perimeter, offering a compact footprint and good thermal and electrical performance through an exposed metal pad often used as a thermal and ground connection. QFN packages require careful reflow soldering profiles because their leads are not visible for inspection after assembly.
Quiescent Current (Iq) — power management term
The current a circuit, typically a voltage regulator, draws internally to operate its control circuitry when delivering little or no current to its load. Low quiescent current is critical in battery-powered and always-on standby applications where the regulator itself must not drain the battery.

R

RTL (Register-Transfer Level) — digital design abstraction level
A design abstraction that describes digital circuit behavior in terms of the flow of data between hardware registers and the logical operations performed on that data, typically written in Verilog or VHDL. RTL is the standard starting point for synthesis into a gate-level netlist in both ASIC and FPGA design flows.
RDS(on) (Drain-Source On-Resistance) — power MOSFET parameter
The resistance between a MOSFET's drain and source terminals when the device is fully turned on, a key figure of merit for conduction losses in power switching applications — lower RDS(on) means less I²R heating and higher efficiency at a given current.
Reflow Soldering — PCB assembly process
The dominant surface-mount assembly process in which solder paste applied to PCB pads is melted in a controlled temperature profile (through a reflow oven) to form permanent solder joints between components and the board, following the profile defined by the solder alloy (commonly lead-free SAC305).
Ripple Voltage — power supply term
The residual periodic variation in a DC voltage that remains after rectification and filtering (or in a switching regulator's output), typically caused by incomplete filtering of the switching frequency or rectified AC component. Excessive ripple can introduce noise into sensitive analog and RF circuits downstream.

S

SerDes (Serializer/Deserializer) — high-speed I/O term
A pair of functional blocks that convert parallel data into a high-speed serial stream for transmission (serializer) and convert it back to parallel form at the receiver (deserializer), used in interfaces such as PCIe, SATA, and Ethernet to reduce the pin count needed for high-bandwidth data transfer.
Setup Time / Hold Time — digital timing terms
Setup time is the minimum interval before a clock edge during which data at a flip-flop's input must remain stable for it to be captured reliably; hold time is the minimum interval after the clock edge that the data must continue to remain stable. Violating either constraint causes a flip-flop to enter an unpredictable metastable state, and both are central checks in static timing analysis (STA).
Signal Integrity (SI) — high-speed design discipline
The engineering discipline concerned with preserving the quality of electrical signals as they travel through PCB traces, connectors, and cables — addressing reflections, crosstalk, attenuation, and jitter — critical for reliable operation of high-speed digital and RF systems.
SoC (System-on-Chip) — IC integration term
A single integrated circuit that combines multiple functional subsystems — such as a processor core, memory, and I/O peripherals — that would traditionally require separate chips, reducing board space, power consumption, and interconnect delay compared to a multi-chip solution.
SPICE (Simulation Program with Integrated Circuit Emphasis) — circuit simulation term
An analog circuit simulation engine, originally developed at UC Berkeley, that solves the nonlinear differential equations describing a circuit's transistor, diode, and passive component models to predict its DC, AC, and transient behavior. Modern commercial and open-source simulators (LTspice, PSpice, ngspice) are all derivatives of the original SPICE engine.
Substrate — semiconductor manufacturing / packaging term
The base material on which an integrated circuit is fabricated (typically a silicon wafer) or, in packaging, the intermediate carrier layer that connects the die to the PCB in a BGA-style package.

T

Threshold Voltage (Vt or Vth) — MOSFET parameter
The minimum gate-to-source voltage required to create a conducting channel and turn a MOSFET on. Vt scales down with process node advancement to reduce switching power, but lower Vt also increases subthreshold leakage current, one of the central trade-offs in modern low-power IC design.
Transconductance (gm) — transistor parameter
The ratio of a change in a transistor's output current to the change in its input (gate or base) voltage that caused it, expressed in siemens (or mA/V), a key figure of merit for a transistor's amplifying capability in analog circuit design.
TVS Diode (Transient Voltage Suppressor) — protection component term
A diode designed to clamp voltage transients (from ESD, lightning-induced surges, or inductive switching) to a safe level within nanoseconds, protecting downstream sensitive components without the slower response time of a conventional Zener diode used for the same purpose.

U

UVLO (Undervoltage Lockout) — power management protection feature
A protection function in a power converter or regulator that disables the output when the input supply voltage falls below a defined threshold, preventing erratic or damaging operation at insufficient supply voltage during power-up or brownout conditions.

V

Verilog / VHDL — hardware description languages
The two dominant hardware description languages used to describe digital logic for simulation and synthesis: Verilog, a C-like syntax standardized as IEEE 1364, and VHDL (VHSIC Hardware Description Language), a more strongly typed, Ada-derived language standardized as IEEE 1076. Both compile to equivalent gate-level netlists and are supported by essentially all ASIC and FPGA toolchains.
Via (PCB Via) — PCB layout term
A plated hole through a printed circuit board that provides an electrical connection between different copper layers. Vias are categorized as through-hole (spanning the full board), blind (connecting an outer layer to an inner layer), or buried (connecting only inner layers), with blind and buried vias enabling denser routing at added fabrication cost.

W

Wafer — semiconductor fabrication term
A thin, circular slice of semiconductor material, most commonly monocrystalline silicon, that serves as the substrate on which hundreds to thousands of individual dies are simultaneously fabricated through repeated lithography, deposition, and etch steps before being diced apart.
Wafer Yield — semiconductor manufacturing metric
The percentage of dies on a fabricated wafer that pass functional and parametric testing and are usable, a critical economic metric in semiconductor manufacturing since defects (from particle contamination, process variation, or design marginality) scale with die area, making yield improvement and die-size reduction central to reducing per-unit cost.

Z

Zener Diode — semiconductor device term
A diode specifically designed to operate in reverse breakdown at a well-defined, stable voltage (the Zener voltage), used as a simple voltage reference or basic overvoltage clamp. Zener breakdown dominates at lower voltages (typically below about 5-6 V), while avalanche breakdown dominates the same physical device's behavior at higher rated voltages.