Learn to design, verify, and bring up real semiconductor and electronics hardware — from device physics and analog/digital fundamentals through FPGA and ASIC design, PCB and high-speed design, power electronics, manufacturing, and test.
21 modules and 5 complete real-project design packages, with worked calculations, a downloadable kit, and a certificate of completion.
Band theory, intrinsic vs. extrinsic semiconductors, doping, charge carriers, the PN junction, and drift vs. diffusion current.
Diodes, BJT/MOSFET biasing, op-amp topologies, negative feedback, active filters, and real-world analog design limits.
Boolean algebra, combinational and sequential logic, finite state machines, CMOS electrical characteristics, and basic timing.
FPGA architecture (LUTs, CLBs, routing fabric), FPGA vs. ASIC trade-offs, the implementation flow, and clock resources.
HDL fundamentals, modeling styles, blocking vs. non-blocking assignment, testbenches, and synthesizable design.
The full RTL-to-GDSII flow, timing closure, physical verification signoff, tape-out, and custom-silicon economics.
Schematic capture, footprints, layer stackup, routing rules, ground/power plane strategy, and DFM considerations.
MCU vs. MPU vs. SoC, memory architecture, core peripherals, interrupt handling, and firmware architecture.
Transmission lines, reflections, crosstalk, ground bounce, power integrity/decoupling, and eye diagrams.
Linear vs. switching regulators, efficiency and thermal design, power sequencing, and battery management basics.
LVDS/DDR/PCIe signaling, differential pair routing, length matching, via stubs, and SI/PI simulation.
Package types (DIP to WLCSP), package parasitics, thermal resistance, and wire-bond vs. flip-chip die attach.
Wafer fabrication, photolithography, doping and deposition/etch, process nodes, and yield economics.
Test plan development, bench vs. production test, ATE basics, boundary scan/JTAG, and reliability testing.
Oscilloscope and logic-analyzer technique, systematic debug methodology, and common failure signatures.
Verification vs. validation, testbench methodology, functional coverage, assertions, and formal verification.
Real diagnostic scenarios — field-only timing faults, power/signal coupling, FPGA sim-vs-hardware bugs, and bus lockups.
A 4-wire RTD instrumentation-amplifier front end — worked gain, filter, and self-heating calculations.
A pipelined FIR filter in Verilog — fixed-point quantization, resource estimate, and a worked timing budget.
Stackup, length matching, fly-by termination, and a worked skew-budget calculation for a DDR3-800 interface.
A coin-cell wireless sensor node — low-power firmware, RF-aware layout, and a worked battery-life calculation.
Buck/LDO topology selection, power sequencing, and a worked efficiency/thermal calculation for an FPGA power tree.
Requirements definition, design reviews, the ECO process, IP licensing, and working with CMs and foundries.
A downloadable kit of 12 real project templates, from a component selection worksheet to an ECO template.
A final data-acquisition-system design assignment, drawing-interpretation and troubleshooting exercises, and your certificate of completion.
12 real project templates — a component & datasheet selection worksheet, a schematic & layout design review checklist, a PCB stackup & impedance target worksheet, a power budget & decoupling worksheet, an IC package & land pattern selection worksheet, an ESD & handling procedure checklist, a bring-up & first-power test checklist, a design verification test plan template, a hardware debug log template, a bill of materials template, an engineering change order (ECO) template, and a design review sign-off checklist. Available for download from Module 20 (Documentation & Resource Kit) once you've unlocked the program.
Coming later: sample Verilog/VHDL project files and video demonstrations. Not included in this release.