Build Your Own Silicon Chip is intended for education, experimentation, prototyping, and preparation of simple ASIC designs targeting a SKY130-compatible open flow. It is a browser-side simulation of an RTL-to-GDSII pipeline — no real Yosys/OpenROAD/Verilator toolchain is executed. Generated outputs must be independently verified before any fabrication submission.
Build Your Own Silicon Chip is a browser-based educational and prototyping platform for designing small digital ASICs. Start from a template — a counter, ALU, UART, FSM, or tiny CPU — write or generate Verilog, simulate it with waveforms, and move through a simulated synthesis, floorplanning, placement, clock-tree synthesis, routing, timing signoff, and physical-verification flow modeled on a SKY130-compatible open-source RTL-to-GDSII process, ending in a downloadable tape-out package.
Every project moves through the same ten-stage pipeline — Spec, Design, Verify, Synthesize, Floorplan, Place, CTS, Route, Signoff, GDSII — visible as a persistent progress bar. Each stage produces structured results (cell counts, timing slack, routed-net counts, DRC status) rather than raw tool output, with an optional plain-language explanation of what that stage does and why it matters.
Because Build Your Own Silicon Chip runs entirely in your browser, the RTL-to-GDSII flow itself (Yosys synthesis, OpenROAD place-and-route, Verilator/Icarus simulation) is simulated: results are deterministic and reproducible from your source code and settings, and every report is clearly labeled as simulated output for education and prototyping — not a real EDA toolchain run.
Beginner Mode offers a drag-and-drop visual block designer — gates, a counter, a D flip-flop, an adder — that compiles automatically to readable Verilog you can always inspect. Engineer Mode exposes the Verilog editor, ports, constraints, and every implementation stage directly. Expert Mode surfaces the underlying generated files (netlist preview, SDC constraints, build manifest) for closer inspection.
Use Build Your Own Silicon Chip to learn the ASIC design flow end to end, prototype a small synchronous digital idea (counters, ALUs, UARTs, simple FSMs, a tiny educational CPU), or produce a structured export package (RTL, testbench, constraints, reports, build manifest) to hand off to a real EDA toolchain. It is not a substitute for production-grade EDA software and does not support analog, RF, multi-clock-domain, or advanced-node designs.
No. Build Your Own Silicon Chip simulates the RTL-to-GDSII flow entirely in your browser for education and prototyping. Every synthesis, floorplan, placement, routing, timing, and verification result is a deterministic estimate, not the output of a real toolchain run. Export your project and use a real flow (e.g. OpenLane/OpenROAD) before any fabrication.
The Tape-Out export package includes a clearly labeled GDSII placeholder documenting the simulated geometry, not a real binary GDSII stream — Build Your Own Silicon Chip does not run a real layout tool. Re-implement the design with a genuine RTL-to-GDSII flow to produce a real GDSII file.
V1 targets a single SKY130-compatible open-source process abstraction. Analog, RF, high-speed SerDes, custom transistor layout, mixed-signal design, and advanced nodes are out of scope.
No — projects are stored locally in your browser (localStorage), matching this site's no-account interactive-tool pattern. Clearing your browser storage will remove your projects.
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