Verification versus validation as genuinely different questions, directed and constrained-random testbench methodology, functional coverage versus code coverage, assertion-based verification, simulation versus formal verification trade-offs, and the regression discipline that keeps a growing test suite honest as a design evolves.
"Did we build the design right?" and "did we build the right design?" sound almost identical, but they are answered by two different disciplines, and a design can pass one cleanly while failing the other. This module is about verification specifically — proving RTL matches its own specification — starting from directed testbenches (Module 5's foundation, gone much deeper here) and building up to constrained-random stimulus generation, where a self-checking scoreboard catches mismatches on scenarios no engineer explicitly thought to write a test for.
From there this module covers why 100% code coverage is not remotely the same claim as thorough functional coverage, how SystemVerilog Assertions express temporal properties a single-cycle check can't, and when formal verification's exhaustive proof is worth its computational cost versus simulation's broader practical reach. It closes on why a verification escape is so expensive specifically in the context of Module 6's ASIC design flow — a bug found after tape-out costs a new mask set and a new fabrication run, not a re-simulation.