A pipelined 24-tap FIR low-pass filter for a 48 kHz, 24-bit ADC stream on a low-cost FPGA — worked accumulator sizing, a timing-budget calculation comparing pipelined vs. naive critical paths, and a reference-model testbench, plus the full board-level design and BOM.
The project brief: a sensor-conditioning application needs a real-time FIR low-pass filter running on a 48 kHz, 24-bit ADC input stream, implemented as a 24-tap filter in the fabric of a small, low-cost FPGA rather than in software on a microcontroller. Getting it right means more than writing the Verilog — it means proving, with numbers, that the pipelined datapath actually closes timing at the target clock, that the fixed-point accumulator is wide enough to never overflow, and that the RTL genuinely matches a software reference model rather than merely looking plausible in a waveform viewer.
This module walks the whole build the way a real digital design engineer would: the transposed-form pipelined multiply-accumulate Verilog structure, a worked fixed-point coefficient quantization and accumulator-sizing calculation, a timing-budget calculation contrasting the pipelined critical path against a naive combinational adder tree, a resource-utilization estimate, the Module 16 verification approach against a software reference model, and the complete board-level design with bill of materials. The full worked numbers and finished design reasoning are part of the unlocked module below.