Number systems and Boolean algebra, Karnaugh-map minimization, combinational building blocks, latches vs. edge-triggered flip-flops, counters and shift registers, Moore/Mealy finite state machines, CMOS electrical characteristics, and the propagation-delay and setup/hold timing every synchronous design lives or dies by.
Digital electronics is where the semiconductor device physics from Module 1 turns into circuits that count, decide, and remember. This module walks from binary number systems and Boolean algebra through Karnaugh-map minimization, into the combinational building blocks — adders, multiplexers, decoders, encoders, comparators — that show up in nearly every real digital design, then into sequential logic: the crucial distinction between a level-sensitive latch and an edge-triggered flip-flop, counters, shift registers, and finite state machine design using the Moore and Mealy models.
The module closes on the electrical reality underneath all of it: how a CMOS gate's complementary pull-up and pull-down networks (built from the same MOSFETs Module 1 introduced) keep static power near zero, and how propagation delay, setup time, and hold time together set the fastest clock a synchronous design can actually run at — a preview of the timing-budget discipline Module 16 formalizes, and the sequential-logic foundation Module 4's FPGA fabric and Module 5's Verilog and VHDL content both build on directly.