Chip-level electronics engineering — FPGA architecture, Verilog vs VHDL, the ASIC design flow from RTL to silicon, how semiconductors are actually manufactured, digital logic fundamentals, signal integrity, and embedded systems architecture (MCU/MPU/SoC).
Build a small combinational circuit from AND/OR/NOT/NAND/NOR/XOR/XNOR gates and see its truth table generated live.
Searchable side-by-side reference of common HDL constructs — module/entity, always/process, if/case, assignment operators — in both languages.
Searchable reference of common integrated circuit package types — DIP, SOIC, QFP, BGA, QFN, CSP — with pin counts and typical uses.
IPC-2221 current-capacity trace width sizing plus IPC-2141 microstrip and stripline characteristic impedance.
Inverting/non-inverting amplifier gain, plus single-pole RC low-pass and high-pass filter cutoff frequency.
Setup/hold slack analysis, maximum clock frequency (Fmax), and a pipeline depth estimator for synchronous digital timing budgets.
Place an LED, resistor, pushbutton, potentiometer, and MCU board, wire them across a virtual breadboard, follow guided project templates, and run a short-circuit check.
A 20-section text reference covering digital logic, Verilog/VHDL, FPGA architecture, the ASIC RTL-to-GDSII flow, semiconductor manufacturing, device physics, analog/power electronics, signal integrity, and embedded systems (MCU/MPU/SoC).
A 40-section, image-first guide tracing a custom RISC processor from RTL through FPGA prototyping, ASIC synthesis, physical design, signoff (timing/power/DRC/LVS), GDSII generation, tape-out, and first-silicon bring-up — with 21 real design-flow diagrams.
A 36-chapter, image-first interactive guide to embedded systems with ATtiny/ATmega/ESP32 — development workflow, firmware architecture, sensor interfacing, motor/relay control, PCB integration, power design and energy harvesting, and wireless IoT connectivity.
Why forward and reverse bias aren't just current running the other way. Side-by-side illustrated comparison of how the depletion region narrows under forward bias and widens under reverse bias — the physical asymmetry that lets diodes rectify AC.
Why the same MOSFET acts like a voltage-controlled resistor in triode and a voltage-controlled current source in saturation — and why the naming is the exact opposite of what BJT experience trains you to expect.
Which MOSFET is "on" at zero gate voltage? Enhancement-mode devices are off by default and need a gate voltage to create a channel; depletion-mode devices are built on by default and need a gate voltage to deplete it.
Skin effect crowds current toward a conductor's own surface, all by itself. Proximity effect is the additional crowding a neighboring conductor's field causes on top of that — which is why tightly packed traces and windings need more than a skin-depth calculation.
Why a couple of picofarads of feedback capacitance between an inverting stage's output and input can act like hundreds of picofarads at the input — and why cascode stages exist specifically to break that multiplication.
Why an amplifier can turn a clean sine into a triangular ramp at high amplitude and frequency — even when the frequency itself is well within its rated bandwidth. A large-signal limit that small-signal bandwidth specs don't capture.
Why a chip still burns power even when it's not switching. Dynamic power (P ≈ C·V²·f) is paid only during transitions — static/leakage power flows continuously just from being powered on, and has grown from negligible to dominant as transistors shrink.
Why an op-amp's gain and bandwidth are locked in an inverse tradeoff. Configure a stage for 10× more closed-loop gain and its usable bandwidth drops to 1/10th — a fixed GBW constant, not an independent, separately-adjustable spec.
A BJT's base needs continuous current to stay on; a MOSFET's gate needs only a one-time charge. Same three-terminal shape, opposite control physics — which is exactly why swapping one for the other means redesigning the drive circuit, not just swapping parts.
The real dividing line isn't "uses 1s and 0s." It's whether the circuit must preserve a signal's exact continuous value, or only has to classify it into a noise-margin-separated zone.
One is a parasitic PNPN thyristor that locks into a sustained low-impedance state until power-cycled; the other is a transient discharge that can physically punch through gate oxide in an instant. ESD can trigger latch-up, but preventing one doesn't prevent the other.
Electronics and digital hardware work is not gated by a single discipline-wide PE license the way civil or electrical power engineering is — instead, the credentials that matter are technician-level certifications (the ETA International CET ladder), manufacturing workmanship standards used across the industry (IPC-A-610), and a solid grounding in digital logic and FPGA fundamentals that underpins chip and board-level design work. This overview covers all three tracks: what each covers, who administers it, and how they fit together.
CET Associate prep: DC and AC circuit theory, diode/BJT/MOSFET fundamentals, digital logic basics, and DMM/oscilloscope test-equipment skills — the entry-level ETA International technician credential.
IPC-A-610 prep: solder joint acceptability classes, common assembly defects, component placement/orientation standards, and ESD handling — the workmanship standard behind Certified IPC Specialist training.
Digital Logic & FPGA Fundamentals prep: Boolean algebra and combinational logic, sequential logic and finite state machines, Verilog/VHDL basics, and FPGA architecture — the assumed-knowledge foundation for chip and board-level digital design.