Learn to design, verify, and bring up real semiconductor and electronics hardware — from device physics and analog/digital fundamentals through FPGA and ASIC design, PCB and high-speed design, power electronics, manufacturing, and test. 21 modules from fundamentals through certification, 5 complete real-project design packages (analog sensor signal conditioning board, FPGA DSP board, high-speed DDR3 memory interface board, embedded IoT sensor node, multi-rail power management board), a 12-template documentation kit, and a certificate of completion. One-time purchase, no account required.
Explore the Full Curriculum →No. NCEES offers FE Electrical and Computer (and the corresponding PE Electrical and Computer exams), which cover general electrical/computer engineering fundamentals — those live in the Electrical Engineering studio's exam-prep track. Semiconductor and digital-electronics work is instead served by technician certifications like the CET, manufacturing standards like IPC-A-610, and fundamentals knowledge in digital logic and FPGA design, which is what this studio's exam prep covers.
It depends on the employer. The CET is not a legal licensing requirement the way a PE stamp is, but it is a widely recognized, employer-valued credential that demonstrates baseline competency — many electronics manufacturers, the U.S. military, and technical schools recognize or require it for technician roles.
Anyone touching PCB assembly quality: solderers, rework technicians, quality inspectors, process engineers, and hardware engineers who need to communicate acceptability requirements to a contract manufacturer. Many employers pay for formal Certified IPC Specialist (CIS) training, which is delivered by IPC-authorized trainers rather than taken as a standalone public exam.
No. It covers vendor-neutral concepts — Boolean algebra, sequential logic, HDL basics, and general FPGA architecture (LUTs, CLBs, routing) — that apply whether you end up working with Xilinx/AMD, Intel/Altera, Lattice, or another vendor's toolchain.
Why forward and reverse bias aren't just current running the other way. Side-by-side illustrated comparison of how the depletion region narrows under forward bias and widens under reverse bias — the physical asymmetry that lets diodes rectify AC.
Why the same MOSFET acts like a voltage-controlled resistor in triode and a voltage-controlled current source in saturation — and why the naming is the exact opposite of what BJT experience trains you to expect.
Which MOSFET is "on" at zero gate voltage? Enhancement-mode devices are off by default and need a gate voltage to create a channel; depletion-mode devices are built on by default and need a gate voltage to deplete it.
Skin effect crowds current toward a conductor's own surface, all by itself. Proximity effect is the additional crowding a neighboring conductor's field causes on top of that — which is why tightly packed traces and windings need more than a skin-depth calculation.
Why a couple of picofarads of feedback capacitance between an inverting stage's output and input can act like hundreds of picofarads at the input — and why cascode stages exist specifically to break that multiplication.
Why an amplifier can turn a clean sine into a triangular ramp at high amplitude and frequency — even when the frequency itself is well within its rated bandwidth. A large-signal limit that small-signal bandwidth specs don't capture.
Why a chip still burns power even when it's not switching. Dynamic power (P ≈ C·V²·f) is paid only during transitions — static/leakage power flows continuously just from being powered on, and has grown from negligible to dominant as transistors shrink.
Why an op-amp's gain and bandwidth are locked in an inverse tradeoff. Configure a stage for 10× more closed-loop gain and its usable bandwidth drops to 1/10th — a fixed GBW constant, not an independent, separately-adjustable spec.
A BJT's base needs continuous current to stay on; a MOSFET's gate needs only a one-time charge. Same three-terminal shape, opposite control physics — which is exactly why swapping one for the other means redesigning the drive circuit, not just swapping parts.
The real dividing line isn't "uses 1s and 0s." It's whether the circuit must preserve a signal's exact continuous value, or only has to classify it into a noise-margin-separated zone.
One is a parasitic PNPN thyristor that locks into a sustained low-impedance state until power-cycled; the other is a transient discharge that can physically punch through gate oxide in an instant. ESD can trigger latch-up, but preventing one doesn't prevent the other.
A 20-section text reference covering digital logic, Verilog/VHDL, FPGA architecture, the ASIC RTL-to-GDSII flow, semiconductor manufacturing, device physics, analog/power electronics, signal integrity, and embedded systems (MCU/MPU/SoC). First 3 free to preview.
A 40-section, image-first guide tracing a custom RISC processor from RTL through FPGA prototyping, ASIC synthesis, physical design, signoff (timing/power/DRC/LVS), GDSII generation, tape-out, and first-silicon bring-up — with 21 real design-flow diagrams. First 3 free to preview.
A 55-figure interactive reader tracing the complete RTL-to-GDSII flow on the open-source SKY130 process — transistors, Verilog, synthesis, floorplanning, placement, routing, timing signoff, and tape-out, illustrated with an 8-bit counter carried end to end plus a 10-design project gallery. First 5 free to preview.
A 36-chapter, image-first interactive guide to embedded systems with ATtiny/ATmega/ESP32 — development workflow, firmware architecture, sensor interfacing, motor/relay control, PCB integration, power design and energy harvesting, and wireless IoT connectivity. First 3 free to preview.